參數(shù)資料
型號(hào)： EP9307-IRZ
廠(chǎng)商： Cirrus Logic, Inc.
英文描述： 432498925
中文描述： ARM9的系統(tǒng)芯片以太網(wǎng)USB顯示器和觸摸屏
文件頁(yè)數(shù)： 7/48頁(yè)
文件大?。?/td> 716K
代理商： EP9307-IRZ
DS667PP3
Copyright 2004 Cirrus Logic (All Rights Reserved)
7
EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
Supports 1/10/100 Mbps transfer rates for
home/small-business/large-business applications
Interfaces to an off-chip PHY through industry
standard Media Independent Interface (MII)
Serial Interfaces (SPI, I
2
S and AC ’97)
The SPI port can be configured as a master or a slave,
supporting the National Semiconductor
, Motorola
and
Texas Instruments
signaling protocols.
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. The I
2
S port can
be configured to support two channel, 24 bit audio.
These ports are multiplexed so that I
2
S port 0 will take
over either the AC'97 pins or the SPI pins. The second
and third I2S ports' serial input and serial output pins are
multiplexed with EGPIO[4,5,6,13]. The clocks supplied in
the first I2S port are also used for the second and third
I2S ports.
Normal Mode: One SPI Port and one AC’97 Port
I
2
S on SSP Mode: One AC’97 Port and up to three I
2
S
Ports
I
2
S on AC’97 Mode: One SPI Port and up to three I
2
S
Ports
Note:
I
2
S may not be output on AC’97 and SSP ports at the
same time.
Raster/LCD Interface
The Raster/LCD interface provides data and interface
signals for a variety of display types. It features fully
programmable video interface timing for non-interlaced
flat panel or dual scan displays. Resolutions up to
1280 x 1024 are supported from a unified SDRAM based
frame buffer. A 16-bit PWM provides control for LCD
panel contrast. LCD specific features include:
Timing and interface signals for digital LCD and TFT
displays
Full programmability for either non-interlaced or dual-
scan color and grayscale flat panel displays
Dedicated data path to SDRAM controller for
improved system performance
Pixel depths of 4, 8, 16, or 18-bits per pixel or 256
levels of grayscale
Hardware Cursor up to 64 x 64 pixels
256 x 18 Color Lookup Table
Hardware Blinking
8-bit interface to low end panel
Table C. Ethernet Media Access Controller Pin Assignments
Pin Mnemonic
Pin Description
MDC
Management Data Clock
MDIO
Management Data I/O
RXCLK
Receive Clock
MIIRXD[3:0]
Receive Data
RXDVAL
Receive Data Valid
RXERR
Receive Data Error
TXCLK
Transmit Clock
MIITXD[3:0]
Transmit Data
TXEN
Transmit Enable
TXERR
Transmit Error
CRS
Carrier Sense
CLD
Collision Detect
Table D. Audio Interfaces Pin Assignment
Pin
Name
Normal Mode
I2S on SSP
Mode
I2S on AC'97
Mode
Pin
Description
Pin Description
Pin Description
SCLK1
SPI Bit Clock
I2S Serial Clock
SPI Bit Clock
SFRM1
SPI Frame Clock I2S Frame Clock
SPI Frame Clock
SSPRX1
SPI Serial Input
I2S Serial Input
SPI Serial Input
SSPTX1
SPI Serial
Output
I2S Serial Output
SPI Serial Output
(No I2S Master
Clock)
ARSTn
AC'97 Reset
AC'97 Reset
I2S Master Clock
ABITCLK AC'97 Bit Clock
AC'97 Bit Clock
I2S Serial Clock
ASYNC
AC'97 Frame
Clock
AC'97 Frame
Clock
I2S Frame Clock
ASDI
AC'97 Serial
Input
AC'97 Serial Input
I2S Serial Input
ASDO
AC'97 Serial
Output
AC'97 Serial
Output
I2S Serial Output
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