參數(shù)資料
型號(hào): EP9307-IRZ
廠商: Cirrus Logic, Inc.
英文描述: 432498925
中文描述: ARM9的系統(tǒng)芯片以太網(wǎng)USB顯示器和觸摸屏
文件頁數(shù): 15/48頁
文件大?。?/td> 716K
代理商: EP9307-IRZ
DS667PP3
Copyright 2004 Cirrus Logic (All Rights Reserved)
15
EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Memory Interface
SDRAM Load Mode Register Cycle
Figure 2
through
Figure 5
define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
Symbol
Min
Typ
Max
Unit
SDCLK high time
t
clk_high
-
(t
HCLK
)/2
-
ns
SDCLK low time
t
clk_low
-
(t
HCLK
)/2
-
ns
SDCLK rise/fall time
t
clkrf
-
3
-
ns
Signal delay from SDCLK rising edge time
t
d
-
8
-
ns
Signal hold from SDCLK rising edge time
t
h
-
4
-
ns
DQMn delay from SDCLK rising edge time
t
DQd
-
6
-
ns
DQMn hold from SDCLK rising edge time
t
DQh
-
6
-
ns
DA valid setup to SDCLK rising edge time
t
DAs
-
2
-
ns
DA valid hold from SDCLK rising edge time
t
DAh
-
2
-
ns
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
SDCLK
SDCSn
RASn
CASn
SDWEn
DQMn
AD
DA
OP-Code
t
clk_high
t
clk_low
t
clkrf
t
d
t
h
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