參數(shù)資料
型號： EP7312-ER-90
廠商： Cirrus Logic, Inc.
英文描述： HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
中文描述： 高性能，低功耗的片上系統(tǒng)的SDRAM和增強數(shù)字音頻接口
文件頁數(shù)： 53/64頁
文件大?。?/td> 1710K
代理商： EP7312-ER-90
DS508PP5
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
53
EP7312
High-Performance, Low-Power System on Chip
M6
VDDIO
Pad power
Digital I/O power, 3.3V
M7
SSITXFR
1
Low
I/O
DAI/CODEC/SSI2 frame sync
M8
DRIVE[1]
2
High /
Low
I/O
PWM drive output
M9
FB[0]
I
PWM feedback input
M10
COL[0]
1
High
O
Keyboard scanner column drive
M11
D[27]
1
Low
I/O
Data I/O
M12
VSSIO
Pad ground
I/O ground
M13
A[23]/DRA[4]
1
Low
O
System byte address / SDRAM address
M14
VDDIO
Pad power
Digital I/O power, 3.3V
M15
A[20]/DRA[7]
1
Low
O
System byte address / SDRAM address
M16
D[21]
1
Low
I/O
Data I/O
N1
nEXTFIQ
I
External fast interrupt input
N2
PE[1]/BOOTSEL[1]
1
Input
I/O
GPIO port E / boot mode select
N3
VSSIO
Pad ground
I/O ground
N4
VDDIO
Pad power
Digital I/O power, 3.3V
N5
PD[5]
1
Low
I/O
GPIO port D
N6
PD[2]
1
Low
I/O
GPIO port D
N7
SSIRXDA
I/O
DAI/CODEC/SSI2 serial data input
N8
ADCCLK
1
Low
O
SSI1 ADC serial clock
N9
SMPCLK
1
Low
O
SSI1 ADC sample clock
N10
COL[2]
1
High
O
Keyboard scanner column drive
N11
D[29]
1
Low
I/O
Data I/O
N12
D[26]
1
Low
I/O
Data I/O
N13
HALFWORD
1
Low
O
Halfword access select output
N14
VSSIO
Pad ground
I/O ground
N15
D[22]
1
Low
I/O
Data I/O
N16
D[23]
1
Low
I/O
Data I/O
P1
VSSRTC
RTC ground
Real time clock ground
P2
RTCOUT
O
Real time clock oscillator output
P3
VSSIO
Pad ground
I/O ground
P4
VSSIO
Pad ground
I/O ground
P5
VDDIO
Pad power
Digital I/O power, 3.3V
P6
VSSIO
Pad ground
I/O ground
P7
VSSIO
Pad ground
I/O ground
P8
VDDIO
Pad power
Digital I/O power, 3.3V
P9
VSSIO
Pad ground
I/O ground
P10
VDDIO
Pad power
Digital I/O power, 3.3V
P11
VSSIO
Pad ground
I/O ground
P12
VSSIO
Pad ground
I/O ground
P13
VDDIO
Pad power
Digital I/O power
P14
VSSIO
Pad ground
I/O ground
P15
D[24]
1
Low
I/O
Data I/O
P16
VDDIO
Pad power
Digital I/O power, 3.3V
R1
RTCIN
I/O
Real time clock oscillator input
R2
VDDIO
Pad power
Digital I/O power, 3.3V
R3
PD[4]
1
Low
I/O
GPIO port D
R4
PD[1]
1
Low
I/O
GPIO port D
Table 22. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Strength
Reset
State
Type
Description
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