參數(shù)資料
型號(hào): EP7312-CV-C
廠商: Cirrus Logic, Inc.
英文描述: HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
中文描述: 高性能,低功率系統(tǒng),片上內(nèi)存和增強(qiáng)的數(shù)字音頻接口
文件頁(yè)數(shù): 21/64頁(yè)
文件大?。?/td> 1710K
代理商: EP7312-CV-C
DS508PP5
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
21
EP7312
High-Performance, Low-Power System on Chip
Static Memory
Figure 7
through
Figure 10
define the timings associated with all phases of the Static Memory. The following table
contains thevalues for thetimings of each of the Static Memory modes.
Parameter
Symbol
Min
Typ
Max
Unit
EXPCLK rising edge to nCS assert delay time
t
CSd
2
8
20
ns
EXPCLK falling edge to nCS deassert hold time
t
CSh
2
7
20
ns
EXPCLK rising edge to A assert delay time
t
Ad
4
9
16
ns
EXPCLK falling edge to A deassert hold time
t
Ah
3
10
19
ns
EXPCLK rising edge to nMWE assert delay time
t
MWd
3
6
10
ns
EXPCLK rising edge to nMWE deassert hold time
t
MWh
3
6
10
ns
EXPCLK falling edge to nMOE assert delay time
t
MOEd
3
7
10
ns
EXPCLK falling edge to nMOE deassert hold time
t
MOEh
2
7
10
ns
EXPCLK falling edge to HALFWORD deassert delay time
t
HWd
2
8
20
ns
EXPCLK falling edge to WORD assert delay time
t
WDd
2
8
16
ns
EXPCLK rising edge to data valid delay time
t
Dv
8
13
21
ns
EXPCLK falling edge to data invalid delay time
t
Dnv
6
15
30
ns
Data setup to EXPCLK falling edge time
t
Ds
-
-
1
ns
EXPCLK falling edge to data hold time
t
Dh
-
-
3
ns
EXPCLK rising edge to WRITE assert delay time
t
WRd
5
11
23
ns
EXPREADY setup to EXPCLK falling edge time
t
EXs
-
-
0
ns
EXPCLK falling edge to EXPREADY hold time
t
EXh
-
-
0
ns
相關(guān)PDF資料
PDF描述
EP7312-EB-90 HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
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