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參數(shù)資料
| 型號： | EP4SGX530KH40C4N |
| 廠商： | Altera |
| 文件頁數(shù)： | 59/82頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 530K 1517HBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB數(shù)： | 21248 |
| 邏輯元件/單元數(shù)： | 531200 |
| RAM 位總計： | 28033024 |
| 輸入/輸出數(shù)： | 744 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1517-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 1517-HBGA（42.5x42.5） |
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1–54
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
Chip-Wide Reset (Dev_CLRn) Specifications
Table 1–41 lists the specifications for the Stratix IV chip-wide reset (Dev_CLRn). This
specifications denote the minimum pulse width of the Dev_CLRn signal required to
clear all the device registers.
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface.
General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are
capable of typical 167 MHz and 1.2 LVCMOS at 100 MHz interfacing frequency with
10 pF load.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
1 Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 1–42 lists the high-speed I/O timing for Stratix IV devices.
Table 1–41. Chip-Wide Reset (DEV_CLRn) Specifications
Description
Min
Typ
Max
Unit
Dev_CLRn
500
—
s
Table 1–42. High-Speed I/O Specifications (1), (2) (Part 1 of 3)
Symbol
Conditions
–2/–2× Speed Grade
–3 Speed Grade
–4 Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fHSCLK_in (input
clock frequency)
True Differential I/O
Standards
Clock boost factor W = 1 to 40
5—
800
5
—
717
5
—
717
MHz
fHSCLK_in (input
clock frequency)
Single Ended I/O
Standards (12)
Clock boost factor W = 1 to 40
5
—
800
5
—
717
5
—
717
MHz
fHSCLK_in (input
clock frequency)
Single Ended I/O
Standards (13)
Clock boost factor W = 1 to 40
5
—
520
5
—
420
5
—
420
MHz
fHSCLK_OUT (output
clock frequency)
—5
—
800
5—
717
5—
717
MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP4SGX530KH40C4NES | 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 1517HBGA 制造商:Altera Corporation 功能描述:IC FPGA 744 I/O 1517HBGA |
| EP4SGX530KH40I3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX530KH40I3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX530KH40I4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX530KH40I4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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