參數(shù)資料
型號： EP4SGX180DF29I3
廠商： Altera
文件頁數(shù)： 11/82頁
文件大?。?/td> 0K
描述： IC STRATIX IV FPGA 180K 780FBGA
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 3
系列： Stratix® IV GX
LAB/CLB數(shù)： 7030
邏輯元件/單元數(shù)： 175750
RAM 位總計： 13954048
輸入/輸出數(shù)： 372
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 780-BBGA
供應商設備封裝： 780-FBGA（29x29）
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–11
Electrical Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Hot Socketing
Table 1–15 lists the hot socketing specifications for Stratix IV devices.
Internal Weak Pull-Up Resistor
Table 1–16 lists the weak pull-up resistor values for Stratix IV devices.
COUTFB
Input capacitance on the dual-purpose clock output and feedback pins
5
pF
CCLK1, CCLK3, CCLK8,
and CCLK10
Input capacitance for dedicated clock input pins
2
pF
Table 1–14. Pin Capacitance for Stratix IV Devices (Part 2 of 2)
Symbol
Description
Value
Unit
Table 1–15. Hot Socketing Specifications for Stratix IV Devices
Symbol
Description
Maximum
IIOPIN (DC)
DC current per I/O pin
300
A
IIOPIN (AC)
AC current per I/O pin
8 mA (1)
I
XCVR-TX (DC)
DC current per transceiver TX pin
100 mA
I
XCVR-RX (DC)
DC current per transceiver RX pin
50 mA
Note to Table 1–15:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Table 1–16. Internal Weak Pull-Up Resistor for Stratix IV Devices (1), (3)
Symbol
Description
Conditions (V)
Value (4)
Unit
RPU
Value of the I/O pin pull-up resistor before
and during configuration, as well as user
mode if the programmable pull-up resistor
option is enabled.
VCCIO = 3.0 ±5% (2)
25
k
VCCIO = 2.5 ±5% (2)
25
k
VCCIO = 1.8 ±5% (2)
25
k
VCCIO = 1.5 ±5% (2)
25
k
VCCIO = 1.2 ±5% (2)
25
k
Notes to Table 1–16:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(3) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is
approximately 25 k
(4) These specifications are valid with ±10% tolerances to cover changes over PVT.
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相關代理商/技術參數(shù)
參數(shù)描述
EP4SGX180DF29I3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX180DF29I4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX180DF29I4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX180FF35C2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX180FF35C2XN 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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