4–82
Altera Corporation
Stratix II GX Device Handbook, Volume 2
October 2007
GIGE Mode
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
Overview chapter in volume 2 of the Stratix II GX
Device Handbook for information about this port.
Clock Multiplier Unit
section in the
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Overview chapter in volume 2 of the Stratix II GX
Device Handbook for information about this port.
Clock Recovery Unit
section in the
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Create rx_locktodata port
to lock the RX PLL to the
received data
Overview chapter in volume 2 of the Stratix II GX
Device Handbook for information about this port.
Clock Recovery Unit
section in the
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Create rx_pll_locked port
to indicate RX PLL is in lock with
the reference clock
Overview chapter in volume 2 of the Stratix II GX
Device Handbook for information about this port.
Clock Recovery Unit
section in the
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Create rx_freqlocked port
to indicate RX PLL is in lock with
the received data
Overview chapter in volume 2 of the Stratix II GX
Device Handbook for information about this port.
Clock Recovery Unit
section in the
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Create rx_signaldetect
port to indicate data input signal
detection
Overview chapter in volume 2 of the Stratix II GX
Device Handbook for information about this port.
Receiver Buffer section in
volume 2 of the
Stratix II GX Device
Handbook.
Table 4–28. MegaWizard Plug-In Manager Options (Page 4 for GIGE Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference