Altera Corporation
4–75
June 2009
Stratix II GX Device Handbook, Volume 1
DC and Switching Characteristics
tMEGABESU
Byte enable setup time
before clock
-9
-10
-11
-13
ps
tMEGABEH
Byte enable hold time
after clock
39
40
43
52
ps
tMEGADATAASU
A port data setup time
before clock
50
52
55
67
ps
tMEGADATAAH
A port data hold time
after clock
243
255
271
325
ps
tMEGAADDRASU A port address setup
time before clock
589
618
657
789
ps
tMEGAADDRAH
A port address hold
time after clock
-347
-365
-388
-465
ps
tMEGADATABSU
B port setup time
before clock
50
52
55
67
ps
tMEGADATABH
B port hold time after
clock
243
255
271
325
ps
tMEGAADDRBSU B port address setup
time before clock
589
618
657
789
ps
tMEGAADDRBH
B port address hold
time after clock
-347
-365
-388
-465
ps
tMEGADATACO1
Clock-to-output delay
when using output
registers
480
715
480
749
480
797
480
957
ps
tMEGADATACO2
Clock-to-output delay
without output
registers
1950
2899
1950
3042
1950
3235
1950
3884
ps
tMEGACLKL
Minimum clock low
time
1250
1312
1395
1675
ps
tMEGACLKH
Minimum clock high
time
1250
1312
1395
1675
ps
tMEGACLR
Minimum clear pulse
width
144
151
160
192
ps
(1)
The M512 block fMAX obtained using the Quartus II software does not necessarily equal to 1/TMEGARC.
(2)
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
(3)
This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–61. M-RAM Block Internal Timing Microparameters (Part 2 of 2)
Note (1)
Symbol
Parameter
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Unit
Min
Max
Min
Max
Min
Max
Min
Max