Altera Corporation
4–57
June 2009
Stratix II GX Device Handbook, Volume 1
DC and Switching Characteristics
50-
Ω RT
2.5
Internal parallel termination with
calibration (50-
Ω setting)
VCCIO = 1.8 V
±30
± 30
%
25-
Ω R
S
1.8
Internal series termination with
calibration (25-
Ω setting)
VCCIO = 1.8 V
±5
±10
%
Internal series termination without
calibration (25-
Ω setting)
VCCIO = 1.8 V
±30
%
50-
Ω R
S
1.8
Internal series termination with
calibration (50-
Ω setting)
VCCIO = 1.8 V
±5
±10
%
Internal series termination without
calibration (50-
Ω setting)
VCCIO = 1.8 V
±30
%
50-
Ω R
T
1.8
Internal parallel termination with
calibration (50-
Ω setting)
VCCIO = 1.8 V
±10
±15
%
50-
Ω RS
1.5
Internal series termination with
calibration (50-
Ω setting)
VCCIO = 1.5 V
±8
±10
%
Internal series termination without
calibration (50-
Ω setting)
VCCIO = 1.5 V
±36
%
50-
Ω RT
1.5
Internal parallel termination with
calibration (50-
Ω setting)
VCCIO = 1.5 V
±10
±15
%
50-
Ω R
S
1.2
Internal series termination with
calibration (50-
Ω setting)
VCCIO = 1.2 V
±8
±10
%
Internal series termination without
calibration (50-
Ω setting)
VCCIO = 1.2 V
±50
%
50-
Ω R
T
1.2
Internal parallel termination with
calibration (50-
Ω setting)
VCCIO = 1.2 V
±10
±15
%
(1)
The resistance tolerance for calibrated SOCT is for the moment of calibration. If the temperature or voltage changes
over time, the tolerance may also change.
(2)
On-chip parallel termination with calibration is only supported for input pins.
Table 4–49. On-Chip Termination Specification for Top and Bottom I/O Banks (Part 2 of 2)
Notes (1), (2)
Symbol
Description
Conditions
Resistance Tolerance
Commercial
Max
Industrial
Max
Unit