參數(shù)資料
型號(hào): EP2S180F1020C3
廠商: Altera
文件頁(yè)數(shù): 661/768頁(yè)
文件大小: 0K
描述: IC STRATIX II FPGA 180K 1020FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 6
系列: Stratix® II
LAB/CLB數(shù): 8970
邏輯元件/單元數(shù): 179400
RAM 位總計(jì): 9383040
輸入/輸出數(shù): 742
電源電壓: 1.15 V ~ 1.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1020-BBGA
供應(yīng)商設(shè)備封裝: 1020-FBGA(33x33)
配用: 544-1701-ND - DSP PRO KIT W/SII EP2S180N
其它名稱: 544-1787
9–2
Altera Corporation
Stratix II Device Handbook, Volume 2
January 2008
IEEE Std. 1149.1 BST Architecture
This chapter discusses how to use the IEEE Std. 1149.1 BST circuitry in
Stratix II and Stratix GX devices, including:
IEEE Std. 1149.1 BST architecture
IEEE Std. 1149.1 boundary-scan register
IEEE Std. 1149.1 BST operation control
I/O Voltage Support in JTAG Chain
IEEE Std. 1149.1 BST circuitry utilization
IEEE Std. 1149.1 BST circuitry disabling
IEEE Std. 1149.1 BST guidelines
Boundary-Scan Description Language (BSDL) support
In addition to BST, you can use the IEEE Std. 1149.1 controller for Stratix II
and Stratix II GX device in-circuit reconfiguration (ICR). However, this
chapter only discusses the BST feature of the IEEE Std. 1149.1 circuitry.
f
For information on configuring Stratix II devices via the IEEE Std. 1149.1
in volume 2 of the Stratix II Device Handbook, or the Configuring Stratix II
& Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device
Handbook.
1
When configuring via IJAG make sure that Stratix II,
Stratix II GX, Stratix, Cyclone II, and Cyclone devices are
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II,
Stratix II GX, Stratix, Cyclone II, and Cyclone devices are in the
18th or further position, configuration fails. This does not affect
SignalTap II or boundary-scan testing.
IEEE Std. 1149.1
BST Architecture
A Stratix II and Stratix II GX device operating in IEEE Std. 1149.1 BST
mode uses four required pins, TDI, TDO, TMS and TCK, and one optional
pin, TRST. The TCK pin has an internal weak pull-down resistor, while the
TDI
, TMS and TRST pins have weak internal pull-ups. The TDO output pin
is powered by VCCIO in I/O bank 4. All of the JTAG input pins are
powered by the 3.3-V VCCPD supply. All user I/O pins are tri-stated
during JTAG configuration.
1
For recommendations on how to connect a JTAG chain with
multiple voltages across the devices in the chain, refer to “I/O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2S180F1020C3GA 制造商:Altera Corporation 功能描述:FPGA Stratix
EP2S180F1020C3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 8970 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2S180F1020C4 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 8970 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2S180F1020C4N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 8970 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2S180F1020C5 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 8970 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256