參數(shù)資料
型號(hào)： EP2AGX45DF25C6N
廠商： Altera
文件頁數(shù)： 60/90頁
文件大小： 0K
描述： IC ARRIA II GX FPGA 45K 572FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 5
系列： Arria II GX
LAB/CLB數(shù)： 1805
邏輯元件/單元數(shù)： 42959
RAM 位總計(jì)： 3517440
輸入/輸出數(shù)： 252
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 572-FBGA
供應(yīng)商設(shè)備封裝： 572-FBGA
Chapter 1: Device Datasheet for Arria II Devices
1–55
Switching Characteristics
December 2013
Altera Corporation
Table 1–45 lists the PLL specifications for Arria II GZ devices when operating in both
the commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (-40° to 100°C).
tCASC_
OUTJITTER_
PERIOD_
DEDCLK
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT
100 MHz)
—
425
ps (p-p)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT
100 MHz)
—
42.5
mUI (p-p)
Notes to Table 1–44:
(1) fIN is limited by the I/O fMAX.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) A high-input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean-clock source, which is
less than 200 ps.
(4) FREF is fIN/N when N = 1.
(5) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–62 on page 1–70.
(7) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 Mhz
Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
Table 1–44. PLL Specifications for Arria II GX Devices (Part 3 of 3)
Symbol
Description
Min
Typ
Max
Unit
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
fIN
Input clock frequency (–3 speed grade)
5
—
717 (1)
MHz
Input clock frequency (–4 speed grade)
5
—
717 (1)
MHz
fINPFD
Input frequency to the PFD
5
—
325
MHz
fVCO
PLL VCO operating range (–3 speed grade)
600
—
1,300
MHz
PLL VCO operating range (–4 speed grade)
600
—
1,300
MHz
tEINDUTY
Input clock or external feedback clock input duty cycle
40
—
60
%
fOUT
Output frequency for internal global or regional clock
(–3 speed grade)
—
700 (2)
MHz
Output frequency for internal global or regional clock
(–4 speed grade)
—
500 (2)
MHz
fOUT_EXT
Output frequency for external clock output (–3 speed grade)
—
717 (2)
MHz
Output frequency for external clock output (–4 speed grade)
—
717 (2)
MHz
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
50
55
%
tFCOMP
External feedback clock compensation time
—
10
ns
tCONFIGPLL
Time required to reconfigure scan chain
—
3.5
—
scanclk
cycles
tCONFIGPHASE
Time required to reconfigure phase shift
—
1
—
scanclk
cycles
fSCANCLK
scanclk frequency
—
100
MHz
tLOCK
Time required to lock from end-of-device configuration or
de-assertion of areset
——
1
ms
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參數(shù)描述
EP2AGX45DF25I3 功能描述:IC ARRIA II GX FPGA 45K 572FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Arria II GX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
EP2AGX45DF25I3N 功能描述:IC ARRIA II GX FPGA 45K 572FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Arria II GX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
EP2AGX45DF25I5 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 1805 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX45DF25I5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 1805 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX45DF29C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 1805 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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