參數(shù)資料
型號: EP20K60EQI208-3ES
元件分類: 電源監(jiān)測
英文描述: Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述: 雙電壓監(jiān)視器集成CPU監(jiān)控
文件頁數(shù): 33/114頁
文件大?。?/td> 1623K
代理商: EP20K60EQI208-3ES
Altera Corporation
25
APEX 20K Programmable Logic Device Family Data Sheet
Note:
(1)
This connection is supported in APEX 20KE devices only.
Product-Term Logic
The product-term portion of the MultiCore architecture is implemented
with the ESB. The ESB can be configured to act as a block of macrocells on
an ESB-by-ESB basis. Each ESB is fed by 32 inputs from the adjacent local
interconnect; therefore, it can be driven by the MegaLAB interconnect or
the adjacent LAB. Also, nine ESB macrocells feed back into the ESB
through the local interconnect for higher performance. Dedicated clock
pins, global signals, and additional inputs from the local interconnect
drive the ESB control signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable register. Figure 13
shows the ESB in product-term mode.
Table 9. APEX 20K Routing Scheme
Source
Destination
Row
I/O Pin
Column
I/O Pin
LE
ESB
Local
Interconnect
MegaLAB
Interconnect
Row
FastTrack
Interconnect
Column
FastTrack
Interconnect
FastRow
Interconnect
Row I/O Pin
v
vvv
Column I/O
Pin
vv
LE
v
vvv
ESB
v
vvv
Local
Interconnect
vv
v
MegaLAB
Interconnect
v
Row
FastTrack
Interconnect
v
Column
FastTrack
Interconnect
vv
FastRow
Interconnect
v
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