參數(shù)資料
型號(hào)： EP20K400ERC240-2
廠商： ALTERA CORP
元件分類(lèi)： PLD
英文描述： LOADABLE PLD, PQFP240
封裝： HEAT SINK, POWER, QFP-240
文件頁(yè)數(shù)： 28/65頁(yè)
文件大?。?/td> 781K
代理商： EP20K400ERC240-2
56
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
particular data word can take many cycles. CAM searches all addresses in
parallel and outputs the address storing a particular word. When a match
is found, a match-found flag is set high. Figure 23 shows the CAM block
diagram.
Figure 23. APEX 20KE CAM Block Diagram
CAM can be used in any application requiring high-speed searches, such
as networking, communications, data compression, and cache
management.
The APEX 20KE on-chip CAM provides faster system performance than
traditional discrete CAM. Integrating CAM and logic into the APEX 20KE
device eliminates off-chip and on-chip delays, improving system
performance.
When in CAM mode, the ESB implements 32-word, 32-bit CAM. Wider or
deeper CAM can be implemented by combining multiple CAMs with
some ancillary logic implemented in LEs. The Quartus software combines
ESBs and LEs automatically to create larger CAMs.
CAM supports writing “don’t-care” bits into words of the memory. The
don’t-care bit can be used as a mask for CAM comparisons; any bit set to
don’t-care has no effect on matches.
The output of the CAM can be encoded or unencoded. When encoded, the
ESB outputs an encoded address of the data’s location. For instance, if the
data is located in address 12, the ESB output is 12. When unencoded, the
ESB uses its 16 outputs to show the location of the data over two clock
cycles. In this case, if the data is located in address 12, the 12th output line
goes high. When using unencoded outputs, two clock cycles are required
to read the output, because a 16-bit output bus is used to show the status
of 32 words.
wraddress[]
data[]
wren
inclock
inclocken
inaclr
data_address[]
match
outclock
outclocken
outaclr
相關(guān)PDF資料
PDF描述
EP20K400ERC240-3 LOADABLE PLD, PQFP240
EP20K400ERI240-1 LOADABLE PLD, PQFP240
EP20K400ERI240-2 LOADABLE PLD, PQFP240
EP20K400ERI240-3 LOADABLE PLD, PQFP240
EP20K400FC672-3X LOADABLE PLD, 3.6 ns, PBGA672
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K400FC672-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-1ES 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA
EP20K400FC672-1X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2ES 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA
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