參數(shù)資料
型號(hào)： EP20K400EQI240-1
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PQFP240
封裝： PLASTIC, QFP-240
文件頁數(shù)： 64/65頁
文件大小： 781K
代理商： EP20K400EQI240-1
30
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect. Each IOE contains a
bidirectional I/O buffer and a register that can be used as either an input
or output register to feed input, output, or bidirectional signals. When
used with a dedicated clock pin, these registers provide exceptional
performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,
66-MHz PCI compliance; JTAG BST support; slew-rate control; and
tri-state buffers. APEX 20KE devices offer enhanced I/O support,
including support for LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and AGP
I/O standards.
The ESB can implement a variety of memory functions, including CAM,
RAM, dual-port RAM, ROM, and first-in-first-out (FIFO) functions.
Embedding the memory directly into the die improves performance and
reduces die area compared to distributed-RAM implementations.
Moreover, the abundance of cascadable ESBs ensures that the APEX 20K
device can implement multiple wide memory blocks for high-density
designs. The ESB’s high speed ensures it can implement small memory
blocks without any speed penalty. The abundance of ESBs ensures that
designers can create as many different-sized memory blocks as the system
requires. Figure 1 shows an overview of the APEX 20K device.
Figure 1. APEX 20K Device Block Diagram
APEX 20K devices provide two dedicated clock pins and four dedicated
input pins that drive register control inputs. These signals ensure efficient
distribution of high-speed, low-skew control signals. These signals use
dedicated routing channels to provide short delays and low skews. Four
of the dedicated inputs drive four global signals. These four global signals
can also be driven by internal logic, providing an ideal solution for a clock
divider or internally generated asynchronous clear signals with high
fan-out.
LUT
Memory
IOE
LUT
Memory
IOE
Product Term
LUT
Memory
IOE
Product Term
FastTrack
Interconnect
Clock Management Circuitry
IOEs support
PCI, GTL+,
SSTL-3, LVDS,
and other
standards.
ClockLock
Four-input LUT
for data path and
DSP functions.
Product-term
integration for
high-speed
control logic and
state machines.
Flexible integration
of embedded
memory, including
CAM, RAM,
ROM, and FIFO
functions.
相關(guān)PDF資料
PDF描述
EP20K400EQI240-2 LOADABLE PLD, PQFP240
EP20K400EQI240-3 LOADABLE PLD, PQFP240
EP20K400ERC240-1 LOADABLE PLD, PQFP240
EP20K400ERC240-2 LOADABLE PLD, PQFP240
EP20K400ERC240-3 LOADABLE PLD, PQFP240
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K400FC672-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K400FC672-1X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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