- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299032 > EP20K400EQI240-1 (ALTERA CORP) LOADABLE PLD, PQFP240 PDF資料下載
參數(shù)資料
| 型號： | EP20K400EQI240-1 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數(shù)： | 50/65頁 |
| 文件大?。?/td> | 781K |
| 代理商： | EP20K400EQI240-1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁
76
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1)
See the Operating Requirements for Altera Devices Data Sheet in this data book.
(2)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6)
Typical values are for TA = 25° C, VCCINT = 2.5 V, and VCCIO = 2.5 V or 3.3 V.
(7)
These values are specified under the APEX 20K device recommended operating conditions, shown in Table 16 on
(8)
The APEX 20K input buffers are compatible with 2.5-V and 3.3-V (LVTTL and LVCMOS). Additionally, the input
buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown in Figure 34 on page 77.
(9)
The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(11) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
(12) Capacitance is sample-tested only.
compliance.
ICC0
VCC supply current (standby)
(All ESBs in power-down mode)
VI = ground, no load, no
toggling inputs, -1 speed
grade
10
mA
VI = ground, no load, no
toggling inputs,
-2, -3 speed grades
5
mA
RCONF
Value of I/O pin pull-up resistor
before and during configuration
20
50
k
30
80
k
Table 18. APEX 20K Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on dedicated
clock pin
VIN = 0 V, f = 1.0 MHz
12
pF
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
8
pF
Table 17. APEX 20K Device DC Operating Conditions (Part 2 of 2)
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP20K400EQI240-2 | LOADABLE PLD, PQFP240 |
| EP20K400EQI240-3 | LOADABLE PLD, PQFP240 |
| EP20K400ERC240-1 | LOADABLE PLD, PQFP240 |
| EP20K400ERC240-2 | LOADABLE PLD, PQFP240 |
| EP20K400ERC240-3 | LOADABLE PLD, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K400FC672-1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K400FC672-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K400FC672-1X | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K400FC672-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K400FC672-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。