參數(shù)資料
型號： EP20K300EQC240-2
廠商： Altera
文件頁數(shù)： 29/117頁
文件大?。?/td> 0K
描述： IC APEX 20KE FPGA 300K 240-PQFP
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 24
系列： APEX-20K®
LAB/CLB數(shù)： 1152
邏輯元件/單元數(shù)： 11520
RAM 位總計： 147456
輸入/輸出數(shù)： 152
門數(shù)： 728000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 240-BFQFP
供應商設備封裝： 240-PQFP（32x32）
Altera Corporation
19
APEX 20K Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications, combinatorial
functions, or wide decoding functions that can take advantage of a
cascade chain. In normal mode, four data inputs from the LAB local
interconnect and the carry-in are inputs to a four-input LUT. The
Quartus II software Compiler automatically selects the carry-in or the
DATA3
signal as one of the inputs to the LUT. The LUT output can be
combined with the cascade-in signal to form a cascade chain through the
cascade-out signal. LEs in normal mode support packed registers.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, accumulators, and
comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT
computes a three-input function; the other generates a carry output. As
shown in Figure 8, the first LUT uses the carry-in signal and two data
inputs from the LAB local interconnect to generate a combinatorial or
registered output. For example, when implementing an adder, this output
is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT
uses the same three signals to generate a carry-out signal, thereby creating
a carry chain. The arithmetic mode also supports simultaneous use of the
cascade chain. LEs in arithmetic mode can drive out registered and
unregistered versions of the LUT output.
The Quartus II software implements parameterized functions that use the
arithmetic mode automatically where appropriate; the designer does not
need to specify how the carry chain will be used.
Counter Mode
The counter mode offers clock enable, counter enable, synchronous
up/down control, synchronous clear, and synchronous load options. The
counter enable and synchronous up/down control signals are generated
from the data inputs of the LAB local interconnect. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. Consequently, if any of the LEs in an LAB use the
counter mode, other LEs in that LAB must be used as part of the same
counter or be used for a combinatorial function. The Quartus II software
automatically places any registers that are not used by the counter into
other LABs.
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相關代理商/技術參數(shù)
參數(shù)描述
EP20K300EQC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K300EQC240-2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1152 Macros 152 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K300EQC240-2XN 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1152 Macros 152 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K300EQC240-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1152 Macro 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K300EQC240-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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