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參數(shù)資料
| 型號： | EP20K100EQI240-2X |
| 廠商： | Altera |
| 文件頁數(shù)： | 96/117頁 |
| 文件大小： | 0K |
| 描述： | IC APEX 20KE FPGA 100K 240-PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | APEX-20K® |
| LAB/CLB數(shù)： | 416 |
| 邏輯元件/單元數(shù)： | 4160 |
| RAM 位總計： | 53248 |
| 輸入/輸出數(shù)： | 183 |
| 門數(shù)： | 263000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 240-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
All APEX 20K devices are reconfigurable and are 100% tested prior to
shipment. As a result, test vectors do not have to be generated for fault
coverage purposes. Instead, the designer can focus on simulation and
design verification. In addition, the designer does not need to manage
inventories of different application-specific integrated circuit (ASIC)
designs; APEX 20K devices can be configured on the board for the specific
functionality required.
APEX 20K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable EPC1, EPC2, and
EPC16 configuration devices, which configure APEX 20K devices via a
serial data stream. Moreover, APEX 20K devices contain an optimized
interface that permits microprocessors to configure APEX 20K devices
serially or in parallel, and synchronously or asynchronously. The interface
also enables microprocessors to treat APEX 20K devices as memory and
configure the device by writing to a virtual memory location, making
reconfiguration easy.
After an APEX 20K device has been configured, it can be reconfigured
in-circuit by resetting the device and loading new data. Real-time changes
can be made during system operation, enabling innovative reconfigurable
computing applications.
APEX 20K devices are supported by the Altera Quartus II development
system, a single, integrated package that offers HDL and schematic design
entry, compilation and logic synthesis, full simulation and worst-case
timing analysis, SignalTap logic analysis, and device configuration. The
Quartus II software runs on Windows-based PCs, Sun SPARCstations,
and HP 9000 Series 700/800 workstations.
The Quartus II software provides NativeLink interfaces to other industry-
standard PC- and UNIX workstation-based EDA tools. For example,
designers can invoke the Quartus II software from within third-party
design tools. Further, the Quartus II software contains built-in optimized
synthesis libraries; synthesis tools can use these libraries to optimize
designs for APEX 20K devices. For example, the Synopsys Design
Compiler library, supplied with the Quartus II development system,
includes DesignWare functions optimized for the APEX 20K architecture.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K100EQI240-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100ERC208-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100ERC208-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100ERC208-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100ERC240-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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