參數(shù)資料
型號： EP20K100
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁數(shù)： 76/117頁
文件大?。?/td> 570K
代理商： EP20K100
76
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Note to
Tables 38
and
39
:
(1)
These timing parameters are sample-tested only.
Table 39. APEX 20KE External Bidirectional Timing Parameters
Note (1)
Symbol
Parameter
Conditions
t
INSUBIDIR
Setup time for bidirectional pins with global clock at LAB adjacent Input
Register
Hold time for bidirectional pins with global clock at LAB adjacent Input
Register
Clock-to-output delay for bidirectional pins with global clock at IOE output
register
Synchronous Output Enable Register to output buffer disable delay
Synchronous Output Enable Register output buffer enable delay
Setup time for bidirectional pins with PLL clock at LAB adjacent Input
Register
Hold time for bidirectional pins with PLL clock at LAB adjacent Input
Register
Clock-to-output delay for bidirectional pins with PLL clock at IOE output
register
Synchronous Output Enable Register to output buffer disable delay with
PLL
Synchronous Output Enable Register output buffer enable delay with PLL
t
INHBIDIR
t
OUTCOBIDIR
C1 = 10 pF
t
XZBIDIR
t
ZXBIDIR
t
INSUBIDIRPLL
C1 = 10 pF
C1 = 10 pF
t
INHBIDIRPLL
t
OUTCOBIDIRPLL
C1 = 10 pF
t
XZBIDIRPLL
C1 = 10 pF
t
ZXBIDIRPLL
C1 = 10 pF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K1000C 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic
EP20K1000CB652C7 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000CB652C7NJ 制造商:Altera Corporation 功能描述:FPGA APEX 20KC Family 1M Gates 38400 Cells 375.94MHz 0.15um (CMOS) Technology 1.8V 652-Pin FCBGA 制造商:Altera Corporation 功能描述:FPGA APEX 20KC Family 1M Gates 38400 Cells 375.94MHz 0.15um Technology 1.8V 652-Pin FCBGA
EP20K1000CB652C8 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000CB652C9 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macro 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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