2–16
Altera Corporation
Stratix GX Device Handbook, Volume 1
June 2006
Figure 2–13. Receiver PLL & CRU Circuit
(1)
m = 8, 10 16, or 20.
The receiver PLLs and CRUs are capable of supporting up to 3.1875 Gbps.
The input clock frequency for –5 and –6 speed grade devices is limited to
650 MHz if you use the REFCLKB pin or 325 MHz if you use the other
clock routing resources. The maximum input clock frequency for –7 speed
grade devices is 312.5 MHz if you use the REFCLKB pin or 156.25 MHz
with the other clock routing resources. An optional RX_LOCKED port
(active low signal) is available to indicate whether the PLL is locked to the
reference clock. The receiver PLL has a programmable loop bandwidth,
which can be set to low, medium, or high. The loop bandwidth parameter
can be statically set by the Quartus II software.
Table 2–5 lists the adjustable parameters of the receiver PLL and CRU. All
the parameters listed are statically programmable in the Quartus II
software.
Dedicated
Local
REFCLKB
÷ 2
PFD
VCO
÷ m (1)
Charge Pump
and Loop Filter
rx_riv[ ]
CRU
Global Clks, IO Bus, Gen Routing
rx_locktorefclk
rx_locktodata
RX_IN
rx_freqlocked[]
High-speed RCVD_CLK
Low-speed RCVD_CLK
Low-Speed TX_PLL_CLK
RX CRUCLK
up
down
up
down
Receiver PLL
Inter Transceiver Routing (IQ2)
rx_locked
Table 2–5. Receiver PLL & CRU Adjustable Parameters (Part 1 of 2)
Parameter
Specifications
Input reference frequency range
25 MHz to 650 MHz
Data rate support
500 Mbps to 3.1875 Gbps