- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299030 > EP1K50QC208 (ALTERA CORP) LOADABLE PLD, PQFP208 PDF資料下載
參數(shù)資料
| 型號(hào)： | EP1K50QC208 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, PQFP208 |
| 封裝： | 30.60 X 30.60 MM, 0.50 MM PITCH, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 8/84頁(yè) |
| 文件大小： | 2224K |
| 代理商： | EP1K50QC208 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)
16
Altera Corporation
ACEX 1K Programmable Logic Family Data Sheet
Preliminary Information
Figure 8. ACEX 1K Logic Element
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the LUT’s
output drives the LE’s output.
The LE has two outputs that drive the interconnect: one drives the local
interconnect, and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The ACEX 1K architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports high-
speed counters and adders, and the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in a LAB and all LABs in the same row. Intensive use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of these chains
should be limited to speed-critical portions of a design.
To LAB Local
Interconnect
Carry-In
Clock
Select
Carry-Out
Look-Up
Table
(LUT)
Clear/
Preset
Logic
Carry
Chain
Cascade
Chain
Cascade-In
Cascade-Out
To FastTrack
Interconnect
Programmable
Register
PRN
CLRN
D
Q
ENA
Register Bypass
data1
data2
data3
data4
labctrl1
labctrl2
labctrl4
labctrl3
Chip-Wide
Reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP1K50QI208 | LOADABLE PLD, PQFP208 |
| EP1K50TC144 | LOADABLE PLD, PQFP144 |
| EP1K50TI144 | LOADABLE PLD, PQFP144 |
| EP1M120FC484-5 | LOADABLE PLD, PBGA484 |
| EP20K100BC196-1 | LOADABLE PLD, PBGA196 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K50QC2081 | 制造商:ALTERA 功能描述:* |
| EP1K50QC208-1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K50QC208-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QC208-1F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QC208-1N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。