參數(shù)資料
型號(hào)： EP1K50QC208-3N
廠商： Altera
文件頁(yè)數(shù)： 23/86頁(yè)
文件大小： 0K
描述： IC ACEX 1K FPGA 50K 208-PQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 144
系列： ACEX-1K®
LAB/CLB數(shù)： 360
邏輯元件/單元數(shù)： 2880
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 147
門(mén)數(shù)： 199000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
其它名稱： 544-1845
EP1K50QC208-3N-ND
Altera Corporation
3
ACEX 1K Programmable Logic Device Family Data Sheet
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■
Software design support and automatic place-and-route provided by
Altera development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
■
Flexible package options are available in 100 to 484 pins, including
the innovative FineLine BGATM packages (see Tables 2 and 3)
■
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic
Notes:
(1)
ACEX 1K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine
BGA packages.
(2)
Devices in the same package are pin-compatible, although some devices have more I/O pins than others. When
planning device migration, use the I/O pins that are common to all devices.
(3)
This option is supported with a 256-pin FineLine BGA package. By using SameFrameTM pin migration, all FineLine
BGA packages are pin-compatible. For example, a board can be designed to support 256-pin and 484-pin FineLine
BGA packages.
Table 2. ACEX 1K Package Options & I/O Pin Count
Device
100-Pin TQFP
144-Pin TQFP
208-Pin PQFP
256-Pin
FineLine BGA
484-Pin
FineLine BGA
EP1K10
66
92
120
136
136 (3)
EP1K30
102
147
171
171 (3)
EP1K50
102
147
186
249
EP1K100
147
186
333
Table 3. ACEX 1K Package Sizes
Device
100-Pin TQFP
144-Pin TQFP
208-Pin PQFP
256-Pin
FineLine BGA
484-Pin
FineLine BGA
Pitch (mm)
0.50
1.0
Area (mm2)
256
484
936
289
529
Length
× width
(mm
× mm)
16
× 16
22
× 22
30.6
× 30.6
17
× 17
23
× 23
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K50QI208-1DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QI208-1F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QI208-1P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QI208-1X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QI208-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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