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參數(shù)資料
| 型號： | EP1K50QC208-3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 15/86頁 |
| 文件大小： | 0K |
| 描述： | IC ACEX 1K FPGA 50K 208-PQFP |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 144 |
| 系列： | ACEX-1K® |
| LAB/CLB數(shù)： | 360 |
| 邏輯元件/單元數(shù)： | 2880 |
| RAM 位總計： | 40960 |
| 輸入/輸出數(shù)： | 147 |
| 門數(shù)： | 199000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 544-1845 EP1K50QC208-3N-ND |
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a 4-input LUT. The compiler automatically selects the carry-
in or the DATA3 signal as one of the inputs to the LUT. The LUT output
can be combined with the cascade-in signal to form a cascade chain
through the cascade-out signal. Either the register or the LUT can be used
to drive both the local interconnect and the FastTrack Interconnect routing
structure at the same time.
The LUT and the register in the LE can be used independently (register
packing). To support register packing, the LE has two outputs; one drives
the local interconnect, and the other drives the FastTrack Interconnect
routing structure. The DATA4 signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a 3-input function can be computed in the LUT, and a
fourth independent signal can be registered. Alternatively, a 4-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect routing structure while the LUT drives
the local interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a 3-input function; the other generates a carry output. As shown
in Figure 11, the first LUT uses the carry-in signal and two data inputs
from the LAB local interconnect to generate a combinatorial or registered
output. For example, in an adder, this output is the sum of three signals:
a
, b, and carry-in. The second LUT uses the same three signals to generate
a carry-out signal, thereby creating a carry chain. The arithmetic mode
also supports simultaneous use of the cascade chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
Two 3-input LUTs are used; one generates the counter data, and the other
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loaded asynchronously with the clear and preset
register control signals without using the LUT resources.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K50QI208-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QI208-1F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QI208-1P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QI208-1X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QI208-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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