參數(shù)資料
型號(hào)： EP1K100
廠商： Electronic Theatre Controls, Inc.
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁(yè)數(shù)： 59/86頁(yè)
文件大?。?/td> 992K
代理商： EP1K100
Altera Corporation
59
ACEX 1K Programmable Logic Device Family Data Sheet
D
13
T
Tables 27
through
29
describe the ACEX 1K external timing parameters
and their symbols.
Notes to tables:
(1)
External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
(2)
Contact Altera Applications for test circuit specifications and test conditions.
(3)
These timing parameters are sample-tested only.
(4)
This parameter is measured with the measurement and test conditions, including load, specified in the
PCI Local
Bus Specification, Revision 2.2.
Table 27. External Reference Timing Parameters
Note (1)
Symbol
Parameter
Conditions
t
DRR
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
(2)
Table 28. External Timing Parameters
Symbol
Parameter
Conditions
t
INSU
t
INH
t
OUTCO
t
PCISU
t
PCIH
t
PCICO
Setup time with global clock at IOE register
Hold time with global clock at IOE register
Clock-to-output delay with global clock at IOE register
Setup time with global clock for registers used in PCI designs
Hold time with global clock for registers used in PCI designs
Clock-to-output delay with global clock for registers used in PCI designs
(3)
(3)
(3)
(3)
,
(4)
(3)
,
(4)
(3)
,
(4)
Table 29. External Bidirectional Timing Parameters
Note (3)
Symbol
Parameter
Conditions
t
INSUBIDIR
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
Clock-to-output delay for bidirectional pins with global clock at IOE register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate = off
t
INHBIDIR
t
OUTCOBIDIR
t
XZBIDIR
t
ZXBIDIR
CI = 35 pF
CI = 35 pF
CI = 35 pF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K100FC256-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-1N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC2563 制造商:Altera Corporation 功能描述:
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