參數(shù)資料
型號(hào)： EP1K100
廠商： Electronic Theatre Controls, Inc.
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁(yè)數(shù)： 3/86頁(yè)
文件大?。?/td> 992K
代理商： EP1K100
Altera Corporation
3
ACEX 1K Programmable Logic Device Family Data Sheet
D
13
T
I
Software design support and automatic place-and-route provided by
Altera development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/ 800 workstations
Flexible package options are available in 100 to 484 pins, including
the innovative FineLine BGA
TM
packages (see
Tables 2
and
3
)
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic
I
I
Notes:
(1)
ACEX 1K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine
BGA packages.
Devices in the same package are pin-compatible, although some devices have more I/ O pins than others. When
planning device migration, use the I/ O pins that are common to all devices.
This option is supported with a 256-pin FineLine BGA package. By using SameFrame
TM
pin migration, all FineLine
BGA packages are pin-compatible. For example, a board can be designed to support 256-pin and 484-pin FineLine
BGA packages.
(2)
(3)
Table 2. ACEX 1K Package Options & I/O Pin Count
Notes (1)
,
(2)
Device
100-Pin TQFP
144-Pin TQFP
208-Pin PQFP
256-Pin
FineLine BGA
484-Pin
FineLine BGA
EP1K10
EP1K30
EP1K50
EP1K100
66
92
102
102
120
147
147
147
136
171
186
186
136
(3)
171
(3)
249
333
Table 3. ACEX 1K Package Sizes
Device
100-Pin TQFP
144-Pin TQFP
208-Pin PQFP
256-Pin
FineLine BGA
484-Pin
FineLine BGA
Pitch (mm)
Area (mm
2
)
Length
×
width
(mm
×
mm)
0.50
256
16
×
16
0.50
484
22
×
22
0.50
936
1.0
289
17
×
17
1.0
529
23
×
23
30.6
×
30.6
相關(guān)PDF資料
PDF描述
EP1K30 Programmable Logic Device Family
EP1K50 Programmable Logic Device Family
EP1S60B1508C5ES Stratix Device Family Data Sheet
EP1S10B1508C6ES Stratix Device Family Data Sheet
EP1S80F1508I5ES Stratix Device Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K100FC256-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-1N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC2563 制造商:Altera Corporation 功能描述:
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