參數(shù)資料
型號(hào): EP1C6T400I7
廠商: Altera Corporation
英文描述: Cyclone FPGA Family
中文描述: 氣旋FPGA系列
文件頁(yè)數(shù): 90/94頁(yè)
文件大?。?/td> 1138K
代理商: EP1C6T400I7
90
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Note to
Tables 59
64
:
(1)
EP1C3 devices do not support the PCI I/O standard.
Table 65
shows the adder delays for the IOE programmable delays. These
delays are controlled with the Quartus II software options listed in the
Parameter column.
1.8-V LVTTL
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
6,606
5,112
4,862
8,380
7,437
6,888
1,175
1,799
1,363
2,115
1,820
1,330
7,267
5,623
5,348
9,218
8,180
7,576
1,292
1,979
1,499
2,326
2,001
1,463
7,927
6,134
5,834
10,055
8,923
8,264
1,409
2,158
1,635
2,537
2,183
1,595
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1.5-V LVTTL
3.3-V PCI
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Table 64. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2)
I/O Standard
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Table 65. Cyclone IOE Programmable Delays on Column Pins
Parameter
Setting
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Decrease input delay to
internal cells
On
Small
Medium
Large
On
3,057
2,212
2,639
3,057
3,057
3,362
2,433
2,902
3,362
3,362
3,668
2,654
3,166
3,668
3,668
ps
ps
ps
ps
ps
Decrease input delay to
input register
Increase delay to output
pin
On
552
607
662
ps
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