參數(shù)資料
型號: EP1C6T400I7
廠商: Altera Corporation
英文描述: Cyclone FPGA Family
中文描述: 氣旋FPGA系列
文件頁數(shù): 15/94頁
文件大小: 1138K
代理商: EP1C6T400I7
Altera Corporation
15
Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 8
shows the carry-select circuitry in an LAB for a 10-bit full adder.
One portion of the LUT generates the sum of two bits using the input
signals and the appropriate carry-in bit; the sum is routed to the output of
the LE. The register can be bypassed for simple adders or used for
accumulator functions. Another portion of the LUT generates carry-out
bits. An LAB-wide carry-in bit selects which chain is used for the addition
of given inputs. The carry-in signal for each chain,
carry-in0
or
carry-in1
, selects the carry-out to carry forward to the carry-in signal of
the next-higher-order bit. The final carry-out signal is routed to an LE,
where it is fed to local, row, or column interconnects.
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