參數(shù)資料
型號: EP1C6T400I6
廠商: Altera Corporation
英文描述: Cyclone FPGA Family
中文描述: 氣旋FPGA系列
文件頁數(shù): 50/94頁
文件大?。?/td> 1138K
代理商: EP1C6T400I6
50
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Figure 32. Cyclone IOE in Bidirectional I/O Configuration
The Cyclone device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
Chip-Wide Reset
OE Register
PRN
D
ENA
V
CCIO
Optional
PCI Clamp
Column or Row
Interconect
ioe_clk[5..0]
Input Register
PRN
D
ENA
Input Pin to
Input Register Delay
or Input Pin to
Logic Array Delay
Input Pin to
Logic Array Delay
Drive Strength Control
Open-Drain Output
Slew Control
sclr/preset
OE
clkout
ce_out
aclr/prn
clkin
ce_in
Output
Pin Delay
Programmable
Pull-Up
Resistor
Bus Hold
CLRN
Q
Output Register
PRN
D
ENA
CLRN
Q
CLRN
Q
V
CCIO
comb_datain
data_in
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