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參數資料
| 型號： | EP1C6T400I6 |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family |
| 中文描述： | 氣旋FPGA系列 |
| 文件頁數： | 42/94頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | EP1C6T400I6 |
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42
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
The external clock outputs do not have their own V
CC
and ground voltage
supplies. Therefore, to minimize jitter, do not place switching I/O pins
next to these output pins. The EP1C3 device in the 100-pin TQFP package
does not have dedicated clock output pins. The EP1C6 device in the
144-pin TQFP package only supports dedicated clock outputs from PLL 1.
Clock Feedback
Cyclone PLLs have three modes for multiplication and/or phase shifting:
■
Zero delay buffer mode
The external clock output pin is phase-
aligned with the clock input pin for zero delay.
Normal mode
If the design uses an internal PLL clock output, the
normal mode compensates for the internal clock delay from the input
clock pin to the IOE registers. The external clock output pin is phase
shifted with respect to the clock input pin if connected in this mode.
The designer defines which internal clock output from the PLL
should be phase-aligned to compensate for internal clock delay.
No compensation mode
In this mode, the PLL will not compensate
for any clock networks.
■
■
Phase Shifting
Cyclone PLLs have an advanced clock shift capability that enables
programmable phase shifts. Designers can enter a phase shift (in degrees
or time units) for each PLL clock output port or for all outputs together in
one shift. Designers can perform phase shifting in time units with a
resolution range of 156 to 417 ps. The finest resolution equals one eighth
of the VCO period. The VCO period is a function of the frequency input
and the multiplication and division factors. Each clock output counter can
choose a different phase of the VCO period from up to eight taps.
Designers can use this clock output counter along with an initial setting
on the post-scale counter to achieve a phase-shift range for the entire
period of the output clock. The phase tap feedback to the m counter can
shift all outputs to a single phase. The Quartus II software automatically
sets the phase taps and counter settings according to the phase shift
entered.
Lock Detect Signal
The lock output indicates that there is a stable clock output signal in phase
with the reference clock. Without any additional circuitry, the lock signal
may toggle as the PLL begins tracking the reference clock. Therefore, the
designer may need to gate the lock signal for use as a system-control
signal.
相關PDF資料 |
PDF描述 |
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| EP1C6T400I7 | Cyclone FPGA Family |
| EP1C6T400I8 | Cyclone FPGA Family |
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| EP1K10 | ACEX 1K Programmable Logic Family(ACEX 1K 系列可編程邏輯) |
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相關代理商/技術參數 |
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| EP1F | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
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| EP1FB3G1S | 制造商:World Products 功能描述:Electromechanical Relay SPDT 25A 12VDC 225Ohm Through Hole |
| EP1F-B3G1T | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1F-B3G1TT | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
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