參數(shù)資料
型號: EP1C6T400C6
廠商: Altera Corporation
英文描述: Cyclone FPGA Family
中文描述: 氣旋FPGA系列
文件頁數(shù): 39/94頁
文件大?。?/td> 1138K
代理商: EP1C6T400C6
Altera Corporation
39
Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 26. Cyclone PLL Global Clock Connections
Notes to
Figure 26
:
(1)
PLL 1 supports one single-ended or LVDS input via pins
CLK0
and
CLK1
.
(2)
PLL2 supports one single-ended or LVDS input via pins
CLK2
and
CLK3
.
(3)
PLL1_OUT
and
PLL2_OUT
support single-ended or LVDS output. If external output is not required, these pins are
available as regular user I/O pins.
(4)
The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the
144-pin TQFP package does not support external clock output from PLL2.
CLK0
CLK1
(1)
PLL1
PLL2
g0
g1
e
g0
g1
e
PLL1_OUT
(3), (4)
CLK2
CLK3
(2)
PLL2_OUT
(3), (4)
G0
G2
G1
G3
G4
G6
G5
G7
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