參數(shù)資料
型號(hào)： EP1C6T400C6
廠(chǎng)商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁(yè)數(shù)： 38/94頁(yè)
文件大?。?/td> 1138K
代理商： EP1C6T400C6
38
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Table 9
shows the PLL features in Cyclone devices.
Figure 25
shows a
Cyclone PLL.
Notes to
Table 9
:
(1)
The
m
counter ranges from 2 to 32. The
n
counter and the post-scale counters range
from 1 to 32.
(2)
The smallest phase shift is determined by the voltage-controlled oscillator (VCO)
period divided by 8.
(3)
For degree increments, Cyclone devices can shift all output frequencies in
increments of 45°. Smaller degree increments are possible depending on the
frequency and divide parameters.
(4)
The EP1C3 device in the 100-pin TQFP package does not support external clock
output. The EP1C6 device in the 144-pin TQFP package does not support external
clock output from PLL2.
Figure 25. Cyclone PLL
Note (1)
Notes to
Figure 25
:
(1)
The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6
device in the 144-pin TQFP package does not support external output from PLL2.
(2)
LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the
CLK0
pin’s
secondary function is
LVDSCLK1p
and the
CLK1
pin’s secondary function is
LVDSCLK1n
. For PLL 2, the
CLK2
pin’s
secondary function is
LVDSCLK2p
and the
CLK3
pin’s secondary function is
LVDSCLK2n
.
(3)
PFD: phase frequency detector.
Figure 26
shows the PLL global clock connections.
Table 9. Cyclone PLL Features
Feature
PLL Support
Clock multiplication and division
Phase shift
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
m
/(
n
×
post-scale counter)
(1)
Down to 156-ps increments
(2)
,
(3)
Yes
2
One differential or one single-ended
(4)
Charge
Pump
VCO
PFD
(3)
Loop
Filter
CLK0 or
LVDSCLK1p
(2)
CLK1 or
LVDSCLK1n
(2)
÷
n
÷
m
t
t
Global clock
Global clock
I/O buffer
÷g0
÷g1
÷e
VCOutput Port
Counters
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