參數(shù)資料
型號: EP1C6T324I7
廠商: Altera Corporation
英文描述: Cyclone FPGA Family
中文描述: 氣旋FPGA系列
文件頁數(shù): 77/94頁
文件大?。?/td> 1138K
代理商: EP1C6T324I7
Altera Corporation
77
Preliminary Information
Cyclone FPGA Family Data Sheet
Internal timing parameters are specified on a speed grade basis
independent of device density.
Tables 44
through
47
show the internal
timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP
blocks, and MultiTrack interconnects.
Table 44. LE Internal Timing Microparameters
Symbol
-6
-7
-8
Unit
Min
Max
Min
Max
Min
Max
t
SU
t
H
t
CO
t
LUT
t
CLR
t
PRE
t
CLKHL
29
12
33
13
37
15
ps
ps
ps
ps
ps
ps
ps
173
454
198
522
224
590
129
129
107
148
148
123
167
167
139
Table 45. IOE Internal Timing Microparameters
Symbol
-6
-7
-8
Unit
Min
Max
Min
Max
Min
Max
t
SU
t
H
t
CO
t
PIN2COMBOUT_R
t
PIN2COMBOUT_C
t
COMBIN2PIN_R
t
COMBIN2PIN_C
t
CLR
t
PRE
t
CLKHL
98
65
107
71
117
78
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
161
1,107
1,112
2,776
2,764
177
1,217
1,223
3,053
3,040
193
1,328
1,334
3,331
3,316
280
280
95
308
308
104
336
336
114
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