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參數(shù)資料
| 型號(hào)： | EP1C6T324I7 |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family |
| 中文描述： | 氣旋FPGA系列 |
| 文件頁數(shù)： | 73/94頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | EP1C6T324I7 |
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Altera Corporation
73
Preliminary Information
Cyclone FPGA Family Data Sheet
Notes to
Tables 23
–
38
:
(1)
See the
Operating Requirements for Altera Devices Data Sheet
.
(2)
Conditions beyond those listed in
Table 23
may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.6 V for input
currents less than 100 mA and periods shorter than 20 ns.
(4)
Maximum V
CC
rise time is 100 ms, and V
CC
must rise monotonically.
(5)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V
CCINT
and V
CCIO
are
powered.
(6)
Typical values are for T
A
= 25
°
C, V
CCINT
= 1.5 V, and V
CCIO
= 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(7)
This value is specified for normal device operation. The value may vary during power-up. This applies for all V
CCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
(8)
Pin pull-up resistance values will lower if an external source drives the pin higher than V
CCIO
.
(9)
Drive strength is programmable according to values in
Table 14 on page 55
.
(10) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels.
(11) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within
±
0.5 pF.
Power
Consumption
Detailed power consumption information for Cyclone devices will be
released when available.
Timing Model
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Cyclone device densities and speed grades. This section
describes and specifies the performance, internal, external, and PLL
timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary.
Table 39
shows the status of the
Cyclone device timing models.
Table 38. Cyclone Device Capacitance
Note (11)
Symbol
Parameter
Typical
Unit
C
IO
C
LVDS
C
VREF
C
DPCLK
C
CLK
Input capacitance for user I/O pin
Input capacitance for dual-purpose LVDS/user I/O pin
Input capacitance for dual-purpose V
REF
/user I/O pin.
Input capacitance for dual-purpose
DPCLK
/user I/O pin.
Input capacitance for CLK pin.
4.0
4.7
12.0
4.4
4.7
pF
pF
pF
pF
pF
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