參數(shù)資料
型號: EP1C6T240I6ES
廠商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 氣旋的FPGA系列數(shù)據(jù)手冊
文件頁數(shù): 46/104頁
文件大?。?/td> 763K
代理商: EP1C6T240I6ES
2–40
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Figure 2–27. Cyclone IOE Structure
Note to
Figure 2–27
:
(1)
There are two paths available for combinatorial inputs to the logic array. Each path
contains a unique programmable delay chain.
The IOEs are located in I/O blocks around the periphery of the Cyclone
device. There are up to three IOEs per row I/O block and up to three IOEs
per column I/O block (column I/O blocks span two columns). The row
I/O blocks drive row, column, or direct link interconnects. The column
I/O blocks drive column interconnects.
Figure 2–28
shows how a row
I/O block connects to the logic array.
Figure 2–29
shows how a column
I/O block connects to the logic array.
Output Register
Output
Combinatorial
input
(1)
Input
OE Register
OE
Input Register
Logic Array
D
Q
D
Q
D
Q
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