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參數(shù)資料
| 型號： | EP1C6T240C8ES |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 氣旋的FPGA系列數(shù)據手冊 |
| 文件頁數(shù)： | 41/104頁 |
| 文件大?。?/td> | 763K |
| 代理商： | EP1C6T240C8ES |
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Altera Corporation
January 2007
2–35
Preliminary
Global Clock Network & Phase-Locked Loops
Clock Multiplication & Division
Cyclone PLLs provide clock synthesis for PLL output ports using
m
/(
n
×
post scale counter) scaling factors. The input clock is divided by
a pre-scale divider,
n
, and is then multiplied by the
m
feedback factor. The
control loop drives the VCO to match f
IN
×
(
m
/
n
). Each output port has
a unique post-scale counter to divide down the high-frequency VCO. For
multiple PLL outputs with different frequencies, the VCO is set to the
least-common multiple of the output frequencies that meets its frequency
specifications. Then, the post-scale dividers scale down the output
frequency for each output port. For example, if the output frequencies
required from one PLL are 33 and 66 MHz, the VCO is set to 330 MHz (the
least-common multiple in the VCO's range).
Each PLL has one pre-scale divider,
n
, that can range in value from 1 to
32. Each PLL also has one multiply divider,
m
, that can range in value
from 2 to 32. Global clock outputs have two post scale G dividers for
global clock outputs, and external clock outputs have an E divider for
external clock output, both ranging from 1 to 32. The Quartus II software
automatically chooses the appropriate scaling factors according to the
input frequency, multiplication, and division values entered.
Dual-Purpose
Clock Pins
DPCLK0
(3)
v
DPCLK1
(3)
v
DPCLK2
v
DPCLK3
v
DPCLK4
v
DPCLK5
(3)
v
DPCLK6
v
DPCLK7
v
Notes to
Table 2–7
:
(1)
EP1C3 devices only have one PLL (PLL 1).
(2)
EP1C3 devices in the 100-pin TQFP package do not have dedicated clock pins
CLK1
and
CLK3
.
(3)
EP1C3 devices in the 100-pin TQFP package do not have the
DPCLK0
,
DPCLK1
, or
DPCLK5
pins.
Table 2–7. Global Clock Network Sources (Part 2 of 2)
Source
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
相關PDF資料 |
PDF描述 |
|---|---|
| EP1C6T240I6ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240I7ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240I8ES | Cyclone FPGA Family Data Sheet |
| EP1C6T256C6ES | Cyclone FPGA Family Data Sheet |
| EP1C6T256C7ES | Cyclone FPGA Family Data Sheet |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP1F | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
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| EP1FB3G1S | 制造商:World Products 功能描述:Electromechanical Relay SPDT 25A 12VDC 225Ohm Through Hole |
| EP1F-B3G1T | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1F-B3G1TT | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
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