- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362733 > EP1C6T144I8ES (Altera Corporation) Cyclone FPGA Family Data Sheet PDF資料下載
參數(shù)資料
| 型號： | EP1C6T144I8ES |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 氣旋的FPGA系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 77/104頁 |
| 文件大?。?/td> | 763K |
| 代理商： | EP1C6T144I8ES |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁當(dāng)前第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
Altera Corporation
January 2007
4–7
Preliminary
Operating Conditions
Table 4–16. Cyclone Device Capacitance
Note (14)
Symbol
Parameter
Typical
Unit
C
IO
Input capacitance for user I/O pin
4.0
pF
C
LVDS
Input capacitance for dual-purpose LVDS/user I/O pin
4.7
pF
C
VREF
Input capacitance for dual-purpose V
REF
/user I/O pin.
12.0
pF
C
DPCLK
Input capacitance for dual-purpose
DPCLK
/user I/O pin.
4.4
pF
C
CLK
Input capacitance for CLK pin.
4.7
pF
Notes to
Tables 4–1
through
4–16
:
(1)
Refer to the
Operating Requirements for Altera Devices Data Sheet
.
(2)
Conditions beyond those listed in
Table 4–1
may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(4)
Maximum V
CC
rise time is 100 ms, and V
CC
must rise monotonically.
(5)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V
CCINT
and V
CCIO
are
powered.
(6)
Typical values are for T
A
= 25
°
C, V
CCINT
= 1.5 V, and V
CCIO
= 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(7)
V
I
= ground, no load, no toggling inputs.
(8)
This value is specified for normal device operation. The value may vary during power-up. This applies for all
V
CCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
(9)
R
CONF
is the measured value of internal pull-up resistance when the I/O pin is tied directly to GND. R
CONF
value
will be lower if an external source drives the pin higher than V
CCIO
.
(10) Pin pull-up resistance values will lower if an external source drives the pin higher than V
CCIO
.
(11) Drive strength is programmable according to values in
Chapter 2, Cyclone Architecture
,
Table 2–11
.
(12) Overdrive is possible when a 1.5 V or 1.8 V and a 2.5 V or 3.3 V input signal feeds an input pin. Turn on “Allow
voltage overdrive” for LVTTL/LVCMOS input pins in the Assignments > Device > Device and Pin Options > Pin
Placement tab when a device has this I/O combination. However, higher leakage current is expected.
(13) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels.
(14) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within
±
0.5 pF.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP1C6T240C6ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240C7ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240C8ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240I6ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240I7ES | Cyclone FPGA Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1F | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1F-B3G1 | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1FB3G1S | 制造商:World Products 功能描述:Electromechanical Relay SPDT 25A 12VDC 225Ohm Through Hole |
| EP1F-B3G1T | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1F-B3G1TT | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。