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參數(shù)資料
| 型號： | EP1C6T144I8ES |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 氣旋的FPGA系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 14/104頁 |
| 文件大?。?/td> | 763K |
| 代理商： | EP1C6T144I8ES |
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2–8
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
preset/load, synchronous clear, synchronous load, and clock enable
control for the register. These LAB-wide signals are available in all LE
modes. The
addnsub
control signal is allowed in arithmetic mode.
The Quartus II software, in conjunction with parameterized functions
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, you can also
create special-purpose functions that specify which LE operating mode to
use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see
Figure 2–6
). The
Quartus II Compiler automatically selects the carry-in or the
data3
signal as one of the inputs to the LUT. Each LE can use LUT chain
connections to drive its combinatorial output directly to the next LE in the
LAB. Asynchronous load data for the register comes from the
data3
input of the LE. LEs in normal mode support packed registers.
Figure 2–6. LE in Normal Mode
Note to
Figure 2–6
:
(1)
This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
data1
data2
data3
cin (from cout
of previous LE)
4-Input
LUT
data4
addnsub (LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
aload
(LAB Wide)
ALD/PRE
ADATA
CLRN
D
Q
ENA
sclear
(LAB Wide)
sload
(LAB Wide)
Register chain
connection
LUT chain
connection
Register
chain output
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
Register Feedback
(1)
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