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參數(shù)資料
| 型號： | EP1C6T144I7ES |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 氣旋的FPGA系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 16/104頁 |
| 文件大?。?/td> | 763K |
| 代理商： | EP1C6T144I7ES |
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2–10
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Figure 2–7. LE in Dynamic Arithmetic Mode
Note to
Figure 2–7
:
(1)
The
addnsub
signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in dynamic arithmetic mode. The carry-select chain uses the
redundant carry calculation to increase the speed of carry functions. The
LE is configured to calculate outputs for a possible carry-in of 0 and carry-
in of 1 in parallel. The
carry-in0
and
carry-in1
signals from a lower-
order bit feed forward into the higher-order bit via the parallel carry chain
and feed into both the LUT and the next portion of the carry chain. Carry-
select chains can begin in any LE within an LAB.
The speed advantage of the carry-select chain is in the parallel pre-
computation of carry chains. Since the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delays between LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This feature allows the Cyclone architecture
to implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
data1
data2
data3
LUT
addnsub
(LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
ALD/PRE
ADATA
CLRN
D
Q
ENA
Re
g
ister chain
connection
LUT
LUT
LUT
Carry-Out1
Carry-Out0
LAB Carry-In
Carry-In0
Carry-In1
(1)
sclear
(LAB Wide)
sload
(LAB Wide)
LUT chain
connection
Re
g
ister
chain output
Row, column, and
direct link routin
g
Row, column, and
direct link routin
g
Local routin
g
aload
(LAB Wide)
Reg
i
ster
F
eedbac
k
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PDF描述 |
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| EP1C6T144I8ES | Cyclone FPGA Family Data Sheet |
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| EP1C6T240C7ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240C8ES | Cyclone FPGA Family Data Sheet |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP1C6T144I7N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1F | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1F-B3G1 | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1FB3G1S | 制造商:World Products 功能描述:Electromechanical Relay SPDT 25A 12VDC 225Ohm Through Hole |
| EP1F-B3G1T | 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY |
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