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參數(shù)資料
| 型號： | EP1C6Q324C8ES |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 氣旋的FPGA系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 57/104頁 |
| 文件大?。?/td> | 763K |
| 代理商： | EP1C6Q324C8ES |
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Altera Corporation
January 2007
2–51
Preliminary
I/O Structure
Slew-Rate Control
The output buffer for each Cyclone device I/O pin has a programmable
output slew-rate control that can be configured for low noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may
introduce noise transients into the system. A slow slew rate reduces
system noise, but adds a nominal delay to rising and falling edges. Each
I/O pin has an individual slew-rate control, allowing the designer to
specify the slew rate on a pin-by-pin basis. The slew-rate control affects
both the rising and falling edges.
Bus Hold
Each Cyclone device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can hold the signal on an I/O pin at its last-driven
state. Since the bus-hold feature holds the last-driven state of the pin until
the next input signal is present, an external pull-up or pull-down resistor
is not necessary to hold a signal level when the bus is tri-stated.
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. The designer can select this feature individually for each I/O
pin. The bus-hold output will drive no higher than V
CCIO
to prevent
overdriving signals. If the bus-hold feature is enabled, the device cannot
use the programmable pull-up option. Disable the bus-hold feature when
the I/O pin is configured for differential signals.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of
approximately 7 k
Ω
to pull the signal level to the last-driven state.
Table 4–15 on page 4–6
gives the specific sustaining current for each
V
CCIO
voltage level driven through this resistor and overdrive current
used to identify the next-driven input level.
The bus-hold circuitry is only active after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Cyclone device I/O pin provides an optional programmable pull-
up resistor during user mode. If the designer enables this feature for an
I/O pin, the pull-up resistor (typically 25 k
Ω
) holds the output to the
V
CCIO
level of the output pin's bank. Dedicated clock pins do not have the
optional programmable pull-up resistor.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP1C6T144C6 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C6T144C6N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C6T144C7 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C6T144C7N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C6T144C8 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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