參數(shù)資料
型號： EP1C6Q256I6ES
廠商： Altera Corporation
英文描述： Cyclone FPGA Family Data Sheet
中文描述： 氣旋的FPGA系列數(shù)據(jù)手冊
文件頁數(shù)： 44/104頁
文件大?。?/td> 763K
代理商： EP1C6Q256I6ES
2–38
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with
a variable duty cycle. This feature is supported on each PLL post-scale
counter (g0, g1, e). The duty cycle setting is achieved by a low- and high-
time count setting for the post-scale dividers. The Quartus II software
uses the frequency input and the required multiply or divide rate to
determine the duty cycle choices.
Control Signals
There are three control signals for clearing and enabling PLLs and their
outputs. You can use these signals to control PLL resynchronization and
the ability to gate PLL output clocks for low-power applications.
The
pllenable
signal enables and disables PLLs. When the
pllenable
signal is low, the clock output ports are driven by ground and all the PLLs
go out of lock. When the
pllenable
signal goes high again, the PLLs
relock and resynchronize to the input clocks. An input pin or LE output
can drive the
pllenable
signal.
The
areset
signals are reset/resynchronization inputs for each PLL.
Cyclone devices can drive these input signals from input pins or from
LEs. When
areset
is driven high, the PLL counters will reset, clearing
the PLL output and placing the PLL out of lock. When driven low again,
the PLL will resynchronize to its input as it relocks.
The
pfdena
signals control the phase frequency detector (PFD) output
with a programmable gate. If you disable the PFD, the VCO will operate
at its last set value of control voltage and frequency with some drift, and
the system will continue running when the PLL goes out of lock or the
input clock disables. By maintaining the last locked frequency, the system
has time to store its current settings before shutting down. You can either
use their own control signal or gated locked status signals to trigger the
pfdena
signal.
f
For more information on Cyclone PLLs, see
Chapter 6, Using PLLs in
Cyclone Devices
.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1C6T144C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6T144C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6T144C7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6T144C7N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6T144C8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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