參數(shù)資料
型號(hào)： EP1C6Q240C8ES
廠商： Altera Corporation
英文描述： Cyclone FPGA Family Data Sheet
中文描述： 氣旋的FPGA系列數(shù)據(jù)手冊(cè)
文件頁(yè)數(shù)： 59/104頁(yè)
文件大?。?/td> 763K
代理商： EP1C6Q240C8ES
Altera Corporation
January 2007
2–53
Preliminary
I/O Structure
and DM pins to support a DDR SDRAM or FCRAM interface. I/O bank
1 can also support a DDR SDRAM or FCRAM interface, however, the
configuration input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3
can also support a DDR SDRAM or FCRAM interface, however, all the
JTAG pins in I/O bank 3 must operate at 2.5 V.
Figure 2–35. Cyclone I/O Banks
Notes (1)
,
(2)
Notes to
Figure 2–35
:
(1)
Figure 2–35
is a top view of the silicon die.
(2)
Figure 2–35
is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
Each I/O bank has its own
VCCIO
pins. A single device can support 1.5-V,
1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a
different standard with different I/O voltages. Each bank also has dual-
purpose
VREF
pins to support any one of the voltage-referenced
standards (e.g., SSTL-3) independently. If an I/O bank does not use
voltage-referenced standards, the V
REF
pins are available as user I/O pins.
I/
O
Ba
nk
2
I/
O
Ba
nk
3
I/
O
Ba
nk 4
I/
O
Ba
nk 1
All I/
O
Ba
nk
s
S
u
pp
o
rt
■
3
.
3
-V LVTTL/LV
CMOS
■
2
.
5
-V LVTTL/LV
CMOS
■
1.8-V LVTTL/LV
CMOS
■
1.
5
-V LV
CMOS
■
LV
DS
■
RSDS
■
SS
TL-
2
C
l
ass
I
a
n
d
II
■
SS
TL-
3
C
l
ass
I
a
n
d
II
I/
O
Ba
nk
3
Al
s
o
S
u
pp
o
rts
t
h
e
3
.
3
-V
PC
I
I/
O
Sta
n
dard
I/
O
Ba
nk 1
Al
s
o
S
u
pp
o
rts
t
h
e
3
.
3
-V
PC
I
I/
O
Sta
n
dard
In
d
ivi
d
u
a
l
P
ow
er
B
u
s
相關(guān)PDF資料
PDF描述
EP1C6Q240I6ES Cyclone FPGA Family Data Sheet
EP1C6Q240I7ES Cyclone FPGA Family Data Sheet
EP1C6Q240I8ES Cyclone FPGA Family Data Sheet
EP1C6Q256C6ES Cyclone FPGA Family Data Sheet
EP1C6Q256C7ES Cyclone FPGA Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1C6Q240C8N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240I7 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240I7N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6T144C6 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6T144C6N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*