參數(shù)資料
型號: EP1C6Q100I7ES
廠商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 氣旋的FPGA系列數(shù)據(jù)手冊
文件頁數(shù): 18/104頁
文件大?。?/td> 763K
代理商: EP1C6Q100I7ES
2–12
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 10 LEs by
linking LABs together automatically. For enhanced fitting, a long carry
chain runs vertically allowing fast horizontal connections to M4K
memory blocks. A carry chain can continue as far as a full column.
Clear & Preset Logic Control
LAB-wide signals control the logic for the register's clear and preset
signals. The LE directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a NOT-
gate push-back technique. Cyclone devices support simultaneous preset/
asynchronous load and clear signals. An asynchronous clear signal takes
precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one preset signal.
In addition to the clear and preset ports, Cyclone devices provide a chip-
wide reset pin (
DEV_CLRn
) that resets all registers in the device. An
option set before compilation in the Quartus II software controls this pin.
This chip-wide reset overrides all other control signals.
MultiTrack
Interconnect
In the Cyclone architecture, connections between LEs, M4K memory
blocks, and device I/O pins are provided by the MultiTrack interconnect
structure with DirectDrive
TM
technology. The MultiTrack interconnect
consists of continuous, performance-optimized routing lines of different
speeds used for inter- and intra-design block connectivity. The Quartus II
Compiler automatically places critical design paths on faster
interconnects to improve design performance.
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
within the device. The MultiTrack interconnect and DirectDrive
technology simplify the integration stage of block-based designing by
eliminating the re-optimization cycles that typically follow design
changes and additions.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and repeatable performance when
相關(guān)PDF資料
PDF描述
EP1C6Q100I8ES Cyclone FPGA Family Data Sheet
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EP1C6Q144C7ES Cyclone FPGA Family Data Sheet
EP1C6Q144C8ES Cyclone FPGA Family Data Sheet
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參數(shù)描述
EP1C6Q240C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C7N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256