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參數(shù)資料
| 型號： | EP1810 |
| 廠商： | Altera Corporation |
| 英文描述： | Classic EPLD Family(典型EPLD系列器件) |
| 中文描述： | 經(jīng)典系列可編程邏輯器件（典型可編程邏輯器件系列器件） |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 227K |
| 代理商： | EP1810 |
970
Altera Corporation
AN 78: Understanding MAX 5000 & Classic Timing
t
SEXP
Shared expander array delay. The delay of a signal through the
AND-NOT
structure of the shared expander product-term array
that is fed back into the logic array. MAX 5000 devices only.
t
ICS
Global clock delay. The delay from the dedicated clock pin to a
register’s clock input.
t
LAC
Logic array control delay. The
AND
array delay for register
control functions such as preset, clear, and output enable.
MAX 5000 devices only.
t
IC
Array clock delay. The delay through a macrocell’s clock
product term to the register’s clock input.
t
CLR
Register clear time. The delay from the assertion of the register’s
asynchronous clear input to the time the register output
stabilizes at logical low.
t
PRE
Register preset time. The delay from the assertion of the
register’s asynchronous preset input to the time the register
output stabilizes at logical high.
t
LAD
Logic array delay. The time a logic signal requires to propagate
through a macrocell’s
AND-OR-XOR
structure.
t
RD
Register delay. The delay from the rising edge of the register’s
clock to the time the data appears at the register output.
MAX 5000 devices only.
t
COMB
Combinatorial buffer delay. The delay from the time when a
combinatorial logic signal bypasses the programmable register
to the time it becomes available at the macrocell output.
MAX 5000 devices only.
t
LATCH
Latch delay. The propagation delay through the programmable
register when
t
LATCH
is configured as a flow-through latch.
MAX 5000 devices only.
t
SU
Register setup time. The time required for a signal to be stable at
the register input before the register clock’s rising edge to
ensure that the register correctly stores the input data.
t
H
Register hold time. The time required for a signal to be stable at
the register input after the register clock’s rising edge to ensure
that the register correctly stores the input data.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1810-20 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:High-Performance 48-Macrocell Devices |
| EP1810-25 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:High-Performance 48-Macrocell Devices |
| EP1810-35 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:High-Performance 48-Macrocell Devices |
| EP1810-45 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:High-Performance 48-Macrocell Devices |
| EP1810EPLD | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:High-Performance 48-Macrocell Devices |
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