參數(shù)資料
型號(hào)： ENC424J600-I/PT
廠商： Microchip Technology
文件頁數(shù)： 17/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 44-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 160
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-TQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁面： 684 (CN2011-ZH PDF)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS39599G-page 111
PIC18F2220/2320/4220/4320
10.5
PORTE, TRISE and LATE
Registers
PORTE is available only in PIC18F4X20 devices.
PIC18F2X20 devices always will read back 0x00 from
PORTE.
For PIC18F4X20 devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/RD, RE1/AN6/WR and RE2/
AN7/CS) are individually configurable as inputs or out-
puts. These pins have Schmitt Trigger input buffers.
When selected as an analog input, these pins will read
as ‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
TRISE controls the direction of the RE pins even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE Con-
figuration
bit
in
Configuration
Register
3H
(CONFIG3H<7>). When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RE3 also
functions as the programming voltage input during
programming.
EXAMPLE 10-5:
INITIALIZING PORTE
FIGURE 10-13:
BLOCK DIAGRAM OF
RE2:RE0 PINS
Note:
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
Note:
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
MOVLW
0x0A
; Configure A/D
MOVWF
ADCON1 ; for digital inputs
MOVLW
0x03
; Value used to
; initialize data
; direction
MOVWF
TRISC
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
Data
Bus
WR LATE
WR TRISE
RD PORTE
Data Latch
TRIS Latch
RD TRISE
Schmitt
Trigger
Input
Buffer
Q
D
CK
Q
D
CK
EN
QD
EN
I/O pin(1)
RD LATE
or
PORTE
To Analog Converter
Note 1:
I/O pins have diode protection to VDD and VSS.
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