參數(shù)資料
型號(hào)： EN29F040
廠商： Electronic Theatre Controls, Inc.
英文描述： 4 Megabit (512K x 8-bit) Flash Memory
中文描述： 4兆位（為512k × 8位）閃存
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 223K
代理商： EN29F040
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
9
EN29F040
Rev. D, Issue Date: 2001/07/05
Any commands written to the chip during the Embedded Erase algorithm are ignored.
T
he system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,
the device returns to reading array data and addresses are no longer latched.
Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in
“AC Characteristics” for parameters, and Chip/Sector Erase Operation Timings for timing waveforms.
Sector Erase Command
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the address of the sector to be erased, and the sector erase command. The Command Definitions table
shows the address and data requirements for the sector erase command sequence.
The device does
not
require the system to preprogram the memory prior to erase. The Embedded Erase
algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations.
This device does not support multiple sector erase commands. Sector Erase operation will
commence immediately after the first 30h command is written. The first sector erase operation must
finish before another sector erase command can be given.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or
DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the
algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC
Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend / Resume Command
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the
sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation
or Embedded Program algorithm. Addresses are “don’t-cares” when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 μs to suspend the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)
Normal read and write timings and command definitions apply. Reading at any address within erase-
suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”
for information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more
information.
相關(guān)PDF資料
PDF描述
EN29F040-45J 4 Megabit (512K x 8-bit) Flash Memory
EN29F040-45JI 4 Megabit (512K x 8-bit) Flash Memory
EN29F040-45P 4 Megabit (512K x 8-bit) Flash Memory
EN29F040-45PI 4 Megabit (512K x 8-bit) Flash Memory
EN29F040-45T 4 Megabit (512K x 8-bit) Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EN29F040-45J 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
EN29F040-45JI 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
EN29F040-45P 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
EN29F040-45PI 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
EN29F040-45T 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:4 Megabit (512K x 8-bit) Flash Memory
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