參數(shù)資料
型號: EMC2103-1-KP-TR
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 模擬信號調(diào)理
中文描述: SPECIALTY ANALOG CIRCUIT, QCC12
封裝: 4 X 4 MM, ROHS COMPLIANT, QFN-12
文件頁數(shù): 59/89頁
文件大?。?/td> 1243K
代理商: EMC2103-1-KP-TR
RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
Revision 0.90 (08-19-08)
62
SMSC EMC2103
DATASHEET
6.25
Fan Spin Up Configuration Register
The Fan Spin Up Configuration Register controls the settings of Spin Up Routine.
Bit 7 - 6 - DRIVE_FAIL_CNT[1:0] - Determines how many update cycles are used for the Drive Fail
detection function as shown in Table 6.40. This circuitry determines whether the fan can be driven to
the desired tach target.
Bit 5 - NOKICK - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the
programmed spin up time before driving it at the programmed level.
‘0’ (default) - The Spin Up Routine will drive the PWM to 100% for 1/4 of the programmed spin up
time before reverting to the programmed spin level.
‘1’ - The Spin Up Routine will not drive the PWM to 100%. It will set the drive at the programmed
spin level for the entire duration of the programmed spin up time.
Table 6.38 Gain Decode
GAIND OR GAINP OR GAINI [1:0]
RESPECTIVE GAIN FACTOR
10
00
1x
01
2x
1
0
4x (default)
11
8x
Table 6.39 Fan Spin Up Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
46h
R/W
Fan Spin Up
Configuration
DRIVE_FAIL
_CNT [1:0]
NOK
ICK
SPIN_LVL[2:0]
SPINUP_TIME
[1:0]
19h
Table 6.40 DRIVE_FAIL_CNT[1:0] Bit Decode
DRIVE_FAIL_CNT[1:0]
NUMBER OF UPDATE PERIODS
10
00
Disabled - the Drive Fail detection circuitry is
disabled
01
16 - the Drive Fail detection circuitry will count for 16
update periods
10
32 - the Drive Fail detection circuitry will count for 32
update periods
11
64 - the Drive Fail detection circuitry will count for 64
update periods
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