參數(shù)資料
型號： EM785842P
廠商： ELAN Microelctronics Corp .
英文描述： 8-BIT MICRO-CONTROLLER
中文描述： 8位微控制器
文件頁數(shù)： 24/45頁
文件大?。?/td> 461K
代理商： EM785842P
EM785840/5841/5842
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
2004/11/10 V1.2
IOCE (Interrupt mask,)
PAGE0 (Interrupt mask)
7
PWM2
R/W-0
Bit 0 ~ Bit 3, Bit 6 : unused
Bit 4(PWM1) : PWM1 one period reach interrupt mask.
Bit 5 (ADI) : ADC conversion complete interrupt mask
0/1
disable/enable interrupt
There are four registers for A/D converter. Use one bit of interrupt control register (IOCE PAGE0 Bit5) for
A/D conversion complete interrupt. The status and control register of A/D (IOCB PAGE1 and RE PAGE0
Bit5) responses the A/D conversion status or takes control on A/D. The A/D data register (RB PAGE1)
stores A/D conversion result.
ADI bit in IOCE PAGE0 register is end of A/D conversion complete interrupt enable/disable. It
enables/disables ADI flag in RE register when A/D conversion is complete. ADI flag indicates the end of an
A/D conversion. The A/D converter sets the interrupt flag, ADI in RE PAGE0 register when a conversion is
complete. The interrupt can be disabled by setting ADI bit in IOCE PAGE0 Bit5 to ‘0’.
The A/D converter has eight analog input channels AD1~AD8 multiplexed into one sample and hold to A/D
module. Reference voltage can be driven from internal power. The A/D converter itself is of an 10-bit
successive approximation type and produces lost significant 8-bit result in the RB PAGE1 and most
significant 2 bit to R7 PAGE1 bit4, bit5. A conversion is initiated by setting a control bit ADST in IOCB
PAGE1 Bit0. Prior to conversion, the appropriate channel must be selected by setting IN0~IN2 bits in RE
register and allowed for enough time to sample data. Every conversion data of A/D need 12-clock cycle
time. The minimum conversion time required is 13 us (73K sample rate). ADST Bit in IOCB PAGE1 Bit0
must be set to begin a conversion.
It will be automatically reset in hardware when conversion is complete. At the end of conversion, the
START bit is cleared and the A/D interrupt is activated if ADI in IOCE PAGE0 Bit5 = 1. ADI will be set
when conversion is complete. It can be reset in software.
If ADI = 0 in IOCE PAGE0 Bit5, when A/D start conversion by setting ADST(IOCB PAGE1 Bit0) =
1 then A/D will continue conversion without stop and hardware won’t reset ADST bit. In this condition,
ADI is deactived. After ADI in IOCE PAGE0 bit5 is set, ADI in RE PAGE0 bit5 will activate again.
To minimum operating current , all biasing circuits in the A/D module that consume DC current are power
down when ADPWR bit in IOCB PAGE1 Bit2 register is a ’0’. When ADPWR bit is a ‘1’, A/D converter
module is operating.
1 2 3 4 5 6 7 8 9 10
6
0
-
5
4
3
X
-
2
X
-
1
X
-
0
X
-
ADI
R/W-0
PWM1
R/W-0
Fig.8 A/D converter timing
Bit 6: Undefined register. Please clear this bit to 0.
Bit 7 (PWM2) : PWM2 interrupt enable bit
0/1
disable/enable interrupt
START
SAMPLE
ADI(IOCE PAGE0 bit5 ) =1
ADI(RE PAGE0 bit 5)
DATA
Clear by software
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