
EM73492
4-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
1
* This specification are subject to be changed without notice.
7.17.1998
GENERAL DESCRIPTION
EM73492 is an advanced single chip CMOS 4-bit micro-controller. It contains 4K-byte ROM, 244-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, two independent 12-bit timer/counters and one data
pointer (DP) for the kernel function, and the EM73492 also contains 6 interrupt sources, 10 I/O ports (including
1 output port , 2 input ports and 7 bidirection ports) and a serial bidirection interface (SIO).
For the application in the telecom product, EM73492 also supports user the beep tone and DTMF function
and there is another additional 512x4 bits RAM for the repertory dailing data storage.
Except low-power consumption and high speed, EM73492 also has sleep and hold mode operation for power
saving function.
EM73492 is suitable for appliaction in telecom products and family appliances.
FEATURES
Operation voltage
Clock source
: 2.2V to 5.5V (clock frequency : 480 KHz to 4 MHz)
: Single clock system available for resonator or crystal and external clock source
by mask option.
: 480K/960K/3.58M/3.84M/4M Hz decided by mask option.
: 110 powerful instructions.
: Up to 2
μ
s for 4 MHz.
: 4K X 8 bits.
: 244 X 4 bits.
: 2 ports (5-bit)
: Pull-up or pull-down resistor available by mask option for input port function.
Pull-up resistor available by mask option for used as sleep releasing port.
: Pull-up resistor available by mask option.
: 1 port (3-bit) (push-up or open-drain type decided by mask option).
: 7 ports (27-bit) (push-pull or open-drain type decided by mask option).
: Two 12-bit timer/counters are programmable for timer, event counter and pulse
width measurement.
Built-in time base counter : 22 stages.
Subroutine nesting
: Up to 13 levels.
Interrupt
: External . . . . . 2 input interrupt sources.
Internal . . . . . . 2 Timer overflow interrupts.
1 Time base interrupt.
1 SIO interrupt.
SIO function
: Serial bidirection interface can transfer 4-bit data in or out by external or internal
clock with falling or rising edge shift mode.
Beep tone function.
DTMF tone function.
Extended RAM of 512 nibbles for repertory dailing data storage.
Power saving function
: Sleep function, CPU hold internal state and stop oscillating.
Hold function, CPU hold internal state and oscillator still working.
Frequency selection
Instruction set
Instruction cycle time
ROM capacity
RAM capacity
Input port
Port 0
Port 14
Output port
Bidirection I/O port
12 bits timer/counter
Patent Number : 75201, 62630, 61007 (R.O.C)
Patent Pending : 83216083 (R.O.C)