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參數(shù)資料
| 型號(hào)： | EL9115IL-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANALOG DELAY LINE TRPL 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 視頻延遲線 |
| 應(yīng)用： | 模擬波速合成，失真控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（5x5） |
| 包裝： | 帶卷 (TR) |
3
FN7441.7
January 12, 2012
AC Electrical Specifications
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
BW -3dB
3dB Bandwidth
0ns Delay Time
122
MHz
BW 0.1dB
0.1dB Bandwidth
0ns Delay Time
60
MHz
SR
Slew Rate
0ns Delay Time
400
V/s
tR - tF
Transient Response Time
20% to 80%, for all delays, 1V step
2.5
ns
VOVER
Voltage Overshoot
For any delay, response to 1V step input
5
%
Glitch
Switching Glitch
Time for o/p to settle after last s_clock edge
100
ns
THD
Total Harmonic Distortion
1VP-P 10MHz sinewave, offset by +0.2V at
mid delay setting
-50
-40
dB
Xt
Hostile Crosstalk
Stimulate G, measure R/B at 1MHz
-80
dB
VN
Output Noise
Gain X2, measured at 75
Ω load
2.5
mVRMS
dt
Nominal Delay Increment
Note 7
1.75
2
2.25
ns
tMAX
Maximum Delay
55
62
70
ns
DELDT
Delay Diff Between Channels
1.6
%
tPD
Propagation Delay
Measured input to output
9.8
ns
tMAX
Max s_clock Frequency
Maximum programming clock speed
10
MHz
t_en_ck
Minimum Separation Between Serial
Enable and Clock
Check enable low edge can occur after
t_en_ck of previous (ignored) clock and up
to before t_en_ck of next (wanted) clock.
Clock edges occurring within t_en_ck of the
enable edge will have uncertain effect.
10
ns
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
7. Delay increment limits are derived by taking Maximum Delay limits and dividing by the number of steps for the device (e.g., the number of steps
for the EL9115 is 31).
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1
VSP
+5V for delay circuitry and input amp
2
RIN
Red channel input, ref GND
3
GND
0V for delay circuitry supply
4
GIN
Green channel input, ref GND
5
VSM
-5V for input amp
6
BIN
Blue channel input, ref GND
7
CENABLE
Chip enable logical +5V enables chip
8
NSENABLE
ENABLE for serial input; enable on low
9
SDATA
Data into registers; logic threshold 1.2V
10
SCLOCK
Clock to enter data; logical; data written on negative edge
11
BOUT
Blue channel output, ref GNDO
12
VSMO
-5V for output buffers
13
GOUT
Green channel output, ref GNDO
14
GNDO
0V reference for input and output buffers
15
ROUT
Red channel output, ref GNDO
16
VSPO
+5V for output buffers
EL9115
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