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16
FN9210.1
October 7, 2005
Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
where f
OSC
is the switching frequency.
Start-Up Sequence
Figure 33 and 34 show a detailed start-up sequence
waveform. For a successful power up, there should be six
peaks at V
CDLY
. When a fault is detected, the device will
latch off until either EN is toggled or the input supply is
recycled.
When the input voltage is higher than 2.5V, an internal
current source starts to charge C
CDLY
to an upper threshold
using a fast ramp followed by a slow ramp. During the initial
slow ramp, the device checks whether there is a fault
condition. If no fault is found, C
CDLY
is discharged after the
first peak and V
REF
turns on.
During the second ramp, the device checks the status of
V
REF
and over temperature. At the peak of the second
ramp, PG output goes low and enables the input protection
PMOS Q1. Q1 is a controlled FET used to prevent in-rush
current into V
BOOST
before V
BOOST
is enabled internally.
Its rate of turn on is controlled by C
o
. When a fault is
detected, M1 will turn off and disconnect the inductor from
V
IN
.
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~V
IN
. Initially the boost is
not enabled so V
BOOST
rises to V
IN
-V
DIODE
through the
output diode. Hence, there is a step at V
BOOST
during this
part of the start-up sequence. If this step is not desirable, an
external PMOS FET can be used to delay the output until the
boost is enabled internally. The delayed output appears at
A
VDD
.
For the EL7586, V
BOOST
and V
LOGIC
soft-start at the
beginning of the third ramp. The soft-start ramp depends on
the value of the C
DLY
capacitor. For C
DLY
of 220nF, the
soft-start time is ~2ms.
The EL7586A is the same as the EL7586 except V
REF
and
V
LOGIC
turn on when input voltage (V
DD
) exceeds 2.5V.
When a fault is detected, the outputs and the input protection
will turn off but V
REF
will stay on.
V
OFF
turns on at the start of the fourth peak. At the fifth
peak, DELB gate goes low to turn on the external PMOS Q4
to generate a delayed V
BOOST
output.
V
ON
is enabled at the beginning of the sixth ramp. A
VDD
,
PG, V
OFF
, DELB and V
ON
are checked at end of this ramp.
Fault Protection
Once the start-up sequence is complete, the voltage on the
C
DLY
capacitor remains at 1.15V until either a fault is
detected or the EN pin is disabled. If a fault is detected, the
voltage on C
DLY
rises to 2.4V at which point the chip is
disabled until the power is recycled or enable is toggled.
Component Selection for Start-Up Sequencing and
Fault Protection
The C
REF
capacitor is typically set at 220nF and is required
to stabilize the V
REF
output. The range of C
REF
is from
22nF to 1μF and should not be more than five times the
capacitor on C
DEL
to ensure correct start-up operation.
The C
DEL
capacitor is typically 220nF and has a usable
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching μA levels.
C
DEL
should be at least 1/5 of the value of C
REF
(See
above). Note with 220nF on C
DEL
the fault time-out will be
typically 50ms and the use of a larger/smaller value will vary
this time proportionally (e.g. 1μF will give a fault time-out
period of typically 230ms).
Fault Sequencing
The EL7586 and EL7586A have advanced fault detection
systems which protects the IC from both adjacent pin shorts
during operation and shorts on the output supplies.
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.
C
OUT
I
RIPPLE
OSC
------------------------------------------------------
≥
EL7586, EL7586A