參數(shù)資料
型號: EL5211IYEZ
廠商: Intersil
文件頁數(shù): 5/18頁
文件大小: 0K
描述: IC OPAMP DUAL R-R 60MHZ 8-HMSOP
標(biāo)準(zhǔn)包裝: 50
放大器類型: 電壓反饋
電路數(shù): 2
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 75 V/µs
增益帶寬積: 32MHz
-3db帶寬: 60MHz
電流 - 輸入偏壓: 2nA
電壓 - 輸入偏移: 3000µV
電流 - 電源: 5mA
電流 - 輸出 / 通道: 65mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 16.5 V,±2.25 V ~ 8.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-VSSOP,8-MSOP(0.118",3.00mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 8-HMSOP
包裝: 管件
產(chǎn)品目錄頁面: 1233 (CN2011-ZH PDF)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY (SINGLE LAYER) TEST BOARD
P
O
WER
DISSIP
A
TION
(W)
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0.350
AMBIENT TEMPERATURE (°C)
0
25
50
75
100
125
85
150
290mW
TSOT5
θ
JA = +345°C/W
FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 34.
0.6
0.5
0.4
0.3
0.2
0.1
0.0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD
483mW
TSOT5
AMBIENT TEMPERATURE (°C)
POW
E
R
DI
SSI
P
A
TI
ON
(W)
0
25
50
75
100
125
85
150
θJA = +207°C/W
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.6
0.4
0.3
0.2
0.1
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
P
O
WE
R
DI
SSI
PATIO
N
(W)
85
486mW
θ
JA
=
+2
06
°C
/W
HM
SO
P8
0.5
FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 36.
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
0.6
0.4
0.3
0.2
0.1
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
P
O
WE
R
DI
SSI
PATIO
N
(W)
85
870mW
θ
JA
=
+1
15
°C
/W
HM
SO
P8
0.8
0.5
0.7
PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
13
FN7119.7
May 7, 2007
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5111, EL5211, and EL5411 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to ground, a 0.1F ceramic capacitor should be
placed from VS+ to pin to VS- pin. A 4.7F tantalum
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7F capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.
EL5111, EL5211, EL5411
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